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Commit 382900645b1f7244d1b29cc851314c3e194c84e3
authorbsekisser <squirmyworms@embarqmail.com>
Sun, 13 Oct 2013 20:01:07 +0000 (16:01 -0400)
committerbsekisser <squirmyworms@embarqmail.com>
Sun, 13 Oct 2013 20:01:07 +0000 (16:01 -0400)
treef69dbef5e47c7c342c14b6bbce4f57e9eedffce9tree | snapshot
parent2c407d6d22473809a431a55b1c6877015c3c9814commit | diff
Message:
sim_core.c: fix implimentation of muls instruction

specification for muls insruction states 2 cycles, not one as implimented.

bug find credit goes to: Shay Green <gblargg@gmail.com>

modified:   sim_core.c
simavr/sim/sim_core.c diff | blob | history | download
simulation of megaAvr microcontrollers