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Commit 3c84d92136c907749bc4b87067e196cf2df1c69c
authorSami Liedes <sliedes@cc.hut.fi>
Sat, 19 Feb 2011 03:35:57 +0000 (05:35 +0200)
committerMichel Pollet <buserror@gmail.com>
Wed, 23 Feb 2011 11:14:55 +0000 (11:14 +0000)
treeb42626634ee5352e2283412aa32468bb855ac5e7tree | snapshot
parent941c7a9b7812b38f04d88a76640bb3df8e0482abcommit | diff
Message:
Fix LD, ST, LPM, STS, MUL to take the correct number of cycles.

They are now the ATMega timings. Need to figure out how to take
ATTiny into account. Before this change they weren't correct for
either.

Signed-off-by: Sami Liedes <sliedes@cc.hut.fi>
simavr/sim/sim_core.c diff | blob | history | download
simulation of megaAvr microcontrollers