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Commit ae52fb327a9b4a792f45760f407b6c7e69b3cf1d
authorbsekisser <squirmyworms@embarqmail.com>
Sat, 22 Mar 2014 12:13:06 +0000 (08:13 -0400)
committerbsekisser <squirmyworms@embarqmail.com>
Sat, 22 Mar 2014 12:36:08 +0000 (08:36 -0400)
tree2951b4625fcc6da7312e9a91a53fc3b8c86465e0tree | snapshot
parent75fcf0807e9666d4a7d1082ed5855b60252750bfcommit | diff
Message:
sim_core: fix rcall instruction cycles...

Based on the instrtiming.elf code and checking the Avr Instruction
 Manual, RCALL was found to be producing incorrect cycle counts.

Atmega; 3, 16-bit pc; 4, 22-bit pc.

Fixed accordingly.

modified:   sim/sim_core.c
simavr/sim/sim_core.c diff | blob | history | download
simulation of megaAvr microcontrollers