Commit eec2e5aae40d0831c385b6f8ff91fac466b4bb7b
authorga <ga@oldell.fish>
Thu, 21 Jan 2021 15:30:19 +0000 (15:30 +0000)
committerga <ga@oldell.fish>
Thu, 21 Jan 2021 15:30:19 +0000 (15:30 +0000)
tree7238f2716d6b6f1907a9f004930f929486ec6904
parent0e03bc6f48b078606b9a970594ee0ef82ffa0117
Message:
Implement the BIN and IPR bits for attinyX5 and change the ADC sample timing
to roughly match the datasheet.  Add a test.  Those MCUs have no UART, so
test.c and test.h have changes to use an alternative method.
7 files changed:
simavr/cores/sim_tinyx5.h
simavr/sim/avr_adc.c
simavr/sim/avr_adc.h
tests/attiny85_adc_test.c [new file with mode: 0644]
tests/test_attiny85_adc_test.c [new file with mode: 0644]
tests/tests.c
tests/tests.h