0d3f95abd5081d99eee487223c01ff31311d3f0b

They lack WGM bits

Signed-off-by: Michel Pollet <buserror@gmail.com>

diff --git a/simavr/sim/avr_timer.c b/simavr/sim/avr_timer.c
index 5d658a5be94201806f648606ad4e509e57a43214..be213384910b2d82709e711bc78fe432d0a7bfc9 100644 (file)
--- a/simavr/sim/avr_timer.c
+++ b/simavr/sim/avr_timer.c
@@ -407,7 +407,8 @@ void avr_timer_init(avr_t * avr, avr_timer_t * p)
        avr_register_vector(avr, &p->overflow);
        avr_register_vector(avr, &p->icr);
 
-       avr_register_io_write(avr, p->wgm[0].reg, avr_timer_write, p);
+       if (p->wgm[0].reg) // these are not present on older AVRs
+               avr_register_io_write(avr, p->wgm[0].reg, avr_timer_write, p);
        avr_register_io_write(avr, p->cs[0].reg, avr_timer_write, p);
 
        // this assumes all the "pending" interrupt bits are in the same