--- /dev/null
+./simavr/cores/sim_megaxm1.c: avr->data[ mcu->lin.r_linbtr] = 0x20;
+./simavr/cores/sim_mega128rfr2.c: * Temporary hack for mangled avr-libc headers
+./simavr/cores/sim_mega324.c:/* borken avr-libc missing these declarations :/ */
+./simavr/cores/sim_mega324.c:// avr->fuse_value.lfuse = avr->fuse[0];
+./simavr/cores/sim_mega324.c:// avr->fuse_value.hfuse = avr->fuse[1];
+./simavr/cores/sim_mega324.c:// avr->fuse_value.efuse = avr->fuse[2];
+./simavr/cores/sim_mega324.c:// uint8_t hfuse = avr->fuse_value.hfuse;
+./simavr/cores/sim_mega324.c:// avr->fuse_value.bootrst = (hfuse & ~FUSE_BOOTRST) != 0;
+./simavr/cores/sim_mega324.c:// avr->fuse_value.bootsz = (((hfuse & ~FUSE_BOOTSZ0) != 0) << 1) | ((hfuse & ~FUSE_BOOTSZ1) != 0);
+./simavr/cores/sim_mega324.c:// switch (avr->fuse_value.bootsz) {
+./simavr/cores/sim_mega324.c:// case 0: avr->fuse_value.bootloader_pages = 32; break;
+./simavr/cores/sim_mega324.c:// case 1: avr->fuse_value.bootloader_pages = 16; break;
+./simavr/cores/sim_mega324.c:// case 2: avr->fuse_value.bootloader_pages = 8; break;
+./simavr/cores/sim_mega324.c:// case 3: avr->fuse_value.bootloader_pages = 4; break;
+./simavr/cores/sim_mega324.c:// uint32_t appEnd = avr->flashend - avr->fuse_value.bootloader_pages * avr->spm_pagesize;
+./simavr/cores/sim_mega324.c:// AVR_LOG(avr, LOG_DEBUG, "HFUSE=0x%02x -> application 0..0x%04x, bootloader: 0x%04x..0x%04x\n", hfuse, appEnd, appEnd + 1, avr->flashend);
+./simavr/cores/sim_mega324.c:// if (avr->fuse_value.bootrst == 0) {
+./simavr/cores/sim_mega324.c:// avr->reset_pc = appEnd + 1;
+./simavr/cores/sim_mega324.c:// avr->pc = avr->reset_pc;
+./simavr/cores/sim_mega324.c:// AVR_LOG(avr, LOG_OUTPUT, "HFUSE=0x%02x -> bootloader reset at 0x%04x\n", hfuse, avr->reset_pc);
+./simavr/cores/sim_mega324.c: // avr->init_fuse_lock = init_fuse_lock;
+./simavr/cores/sim_mega324.c: // avr->init_fuse_lock(avr);
+./simavr/sim/sim_io.c: avr_io_t * port = avr->io_port;
+./simavr/sim/sim_io.c: io->next = avr->io_port;
+./simavr/sim/sim_io.c: avr->io_port = io;
+./simavr/sim/sim_io.c: if (avr->io[a].r.param || avr->io[a].r.c) {
+./simavr/sim/sim_io.c: if (avr->io[a].r.param != param || avr->io[a].r.c != readp) {
+./simavr/sim/sim_io.c: avr->io[a].r.c, avr->io[a].r.param, readp, param);
+./simavr/sim/sim_io.c: avr->io[a].r.param = param;
+./simavr/sim/sim_io.c: avr->io[a].r.c = readp;
+./simavr/sim/sim_io.c: for (int i = 0; i < avr->io_shared_io[io].used; i++) {
+./simavr/sim/sim_io.c: avr_io_write_t c = avr->io_shared_io[io].io[i].c;
+./simavr/sim/sim_io.c: c(avr, addr, v, avr->io_shared_io[io].io[i].param);
+./simavr/sim/sim_io.c: if (avr->io[a].w.param || avr->io[a].w.c) {
+./simavr/sim/sim_io.c: if (avr->io[a].w.param != param || avr->io[a].w.c != writep) {
+./simavr/sim/sim_io.c: if (avr->io[a].w.c != _avr_io_mux_write) {
+./simavr/sim/sim_io.c: int no = avr->io_shared_io_count++;
+./simavr/sim/sim_io.c: if (avr->io_shared_io_count > ARRAY_SIZE(avr->io_shared_io)) {
+./simavr/sim/sim_io.c: avr->io_shared_io[no].used = 1;
+./simavr/sim/sim_io.c: avr->io_shared_io[no].io[0].param = avr->io[a].w.param;
+./simavr/sim/sim_io.c: avr->io_shared_io[no].io[0].c = avr->io[a].w.c;
+./simavr/sim/sim_io.c: avr->io[a].w.param = (void*)(intptr_t)no;
+./simavr/sim/sim_io.c: avr->io[a].w.c = _avr_io_mux_write;
+./simavr/sim/sim_io.c: int no = (intptr_t)avr->io[a].w.param;
+./simavr/sim/sim_io.c: int d = avr->io_shared_io[no].used++;
+./simavr/sim/sim_io.c: if (avr->io_shared_io[no].used > ARRAY_SIZE(avr->io_shared_io[0].io)) {
+./simavr/sim/sim_io.c: avr->io_shared_io[no].io[d].param = param;
+./simavr/sim/sim_io.c: avr->io_shared_io[no].io[d].c = writep;
+./simavr/sim/sim_io.c: avr->io[a].w.param = param;
+./simavr/sim/sim_io.c: avr->io[a].w.c = writep;
+./simavr/sim/sim_io.c: avr_io_t * port = avr->io_port;
+./simavr/sim/sim_io.c: if (avr->io[a].irq == NULL) {
+./simavr/sim/sim_io.c: avr->io[a].irq = avr_alloc_irq(&avr->irq_pool, 0, 9, namep);
+./simavr/sim/sim_io.c: avr->io[a].irq[i].flags |= IRQ_FLAG_FILTERED;
+./simavr/sim/sim_io.c: free((void*)avr->io[a].irq[index].name);
+./simavr/sim/sim_io.c: avr->io[a].irq[index].name = strdup(n);
+./simavr/sim/sim_io.c: return avr->io[a].irq + index;
+./simavr/sim/sim_io.c:// strcpy(dst, io->avr->mmcu);
+./simavr/sim/sim_io.c: irqs = avr_alloc_irq(&io->avr->irq_pool, 0,
+./simavr/sim/sim_io.c: avr_io_t * port = avr->io_port;
+./simavr/sim/sim_io.c: avr->io_port = NULL;
+./simavr/sim/avr_uart.c: uint8_t st = avr->data[addr];
+./simavr/sim/avr_uart.c: avr->data[addr] = st;
+./simavr/sim/avr_uart.c: avr->data[addr] = 0;
+./simavr/sim/avr_uart.c: ((avr->cycle-p->rxc_raise_time)/p->rx_cnt < p->cycles_per_byte)) {
+./simavr/sim/avr_uart.c: avr->data[addr] = v;
+./simavr/sim/avr_uart.c: double baud = ((double)avr->frequency) / cycles_per_bit; // can be less than 1
+./simavr/sim/avr_uart.c: if (avr->gdb) {
+./simavr/sim/sim_interrupts.c: avr_int_table_p table = &avr->interrupts;
+./simavr/sim/sim_interrupts.c: avr_init_irq(&avr->irq_pool, table->irq,
+./simavr/sim/sim_interrupts.c: avr_int_table_p table = &avr->interrupts;
+./simavr/sim/sim_interrupts.c: avr->interrupt_state = 0;
+./simavr/sim/sim_interrupts.c: avr_int_table_p table = &avr->interrupts;
+./simavr/sim/sim_interrupts.c: avr_init_irq(&avr->irq_pool, vector->irq,
+./simavr/sim/sim_interrupts.c: avr_int_table_p table = &avr->interrupts;
+./simavr/sim/sim_interrupts.c: vector->vector, !!avr->sreg[S_I], avr_regbit_get(avr, vector->enable),
+./simavr/sim/sim_interrupts.c: (long long int)avr->cycle, avr->pc);
+./simavr/sim/sim_interrupts.c: avr_raise_irq(avr->interrupts.irq + AVR_INT_IRQ_PENDING, vector->vector);
+./simavr/sim/sim_interrupts.c: avr_int_table_p table = &avr->interrupts;
+./simavr/sim/sim_interrupts.c: if (avr->sreg[S_I] && avr->interrupt_state == 0)
+./simavr/sim/sim_interrupts.c: avr->interrupt_state = 1;
+./simavr/sim/sim_interrupts.c: if (avr->state == cpu_Sleeping) {
+./simavr/sim/sim_interrupts.c: avr->state = cpu_Running; // in case we were sleeping
+./simavr/sim/sim_interrupts.c: avr_raise_irq_float(avr->interrupts.irq + AVR_INT_IRQ_PENDING,
+./simavr/sim/sim_interrupts.c: &avr->interrupts.pending, 0)->vector : 0,
+./simavr/sim/sim_interrupts.c: avr_raise_irq(avr->interrupts.irq + AVR_INT_IRQ_PENDING,
+./simavr/sim/sim_interrupts.c: avr_int_table_p table = &avr->interrupts;
+./simavr/sim/sim_interrupts.c: avr_int_table_p table = &avr->interrupts;
+./simavr/sim/sim_interrupts.c: if (!avr->sreg[S_I] || !avr->interrupt_state)
+./simavr/sim/sim_interrupts.c: if (avr->interrupt_state < 0) {
+./simavr/sim/sim_interrupts.c: avr->interrupt_state++;
+./simavr/sim/sim_interrupts.c: if (avr->interrupt_state == 0)
+./simavr/sim/sim_interrupts.c: avr->interrupt_state = avr_has_pending_interrupts(avr);
+./simavr/sim/sim_interrupts.c: avr_int_table_p table = &avr->interrupts;
+./simavr/sim/sim_interrupts.c: avr->interrupt_state = avr_has_pending_interrupts(avr);
+./simavr/sim/sim_interrupts.c: _avr_push_addr(avr, avr->pc);
+./simavr/sim/sim_interrupts.c: avr->pc = vector->vector * avr->vector_size;
+./simavr/sim/avr_adc.c: avr->data[p->r_adcl] = p->result & 0xff;
+./simavr/sim/avr_adc.c: avr->data[p->r_adch] = p->result >> 8;
+./simavr/sim/avr_adc.c: if ( !avr->vcc) {
+./simavr/sim/avr_adc.c: reg = avr->vcc / 4;
+./simavr/sim/avr_adc.c: if (!avr->vcc)
+./simavr/sim/avr_adc.c: vref = avr->vcc;
+./simavr/sim/avr_adc.c: if (!avr->aref)
+./simavr/sim/avr_adc.c: vref = avr->aref;
+./simavr/sim/avr_adc.c: if (!avr->avcc)
+./simavr/sim/avr_adc.c: vref = avr->avcc;
+./simavr/sim/avr_adc.c: v |= (mask & avr->data[p->adsc.reg]);
+./simavr/sim/avr_adc.c: avr->data[p->adsc.reg] = v;
+./simavr/sim/avr_adc.c: v = avr->data[p->adsc.reg];
+./simavr/sim/avr_adc.c: AVR_LOG(avr, LOG_TRACE, "ADC: Start AREF %d AVCC %d\n", avr->aref, avr->avcc);
+./simavr/sim/avr_adc.c: v = avr->data[p->adsc.reg]; // Peter Ross pross@xvid.org
+./simavr/sim/avr_adc.c: (avr->frequency >> div) / 13 / 100);
+./simavr/sim/avr_adc.c: uint8_t val = avr->data[addr] | (1 << p->adsc.bit);
+./simavr/sim/avr_timer.c: return p->io.avr->data[p->comp[compi].r_ocr] |
+./simavr/sim/avr_timer.c: (p->io.avr->data[p->comp[compi].r_ocrh] << 8) : 0);
+./simavr/sim/avr_timer.c: return avr->data[comp->r_ocr] |
+./simavr/sim/avr_timer.c: (ocrh ? (avr->data[ocrh] << 8) : 0);
+./simavr/sim/avr_timer.c: return p->io.avr->data[p->r_tcnt] |
+./simavr/sim/avr_timer.c: (p->r_tcnth ? (p->io.avr->data[p->r_tcnth] << 8) : 0);
+./simavr/sim/avr_timer.c: return p->io.avr->data[p->r_icr] |
+./simavr/sim/avr_timer.c: (p->r_tcnth ? (p->io.avr->data[p->r_icrh] << 8) : 0);
+./simavr/sim/avr_timer.c: dispatch[compi](avr, avr->cycle, param);
+./simavr/sim/avr_timer.c: if (p->comp[compi].comp_cycles < p->tov_cycles && p->comp[compi].comp_cycles >= (avr->cycle - when)) {
+./simavr/sim/avr_timer.c: p->comp[compi].comp_cycles - (avr->cycle - next),
+./simavr/sim/avr_timer.c: uint64_t when = avr->cycle - p->tov_base;
+./simavr/sim/avr_timer.c: avr->data[p->r_tcnt] = tcnt;
+./simavr/sim/avr_timer.c: avr->data[p->r_tcnth] = tcnt >> 8;
+./simavr/sim/avr_timer.c: avr_timer_tov(avr, avr->cycle - cycles, p);
+./simavr/sim/avr_timer.c: // tcnt = ((avr->cycle - p->tov_base) * p->tov_top) / p->tov_cycles;
+./simavr/sim/avr_timer.c: resulting_clock = (float)avr->frequency / prescaler;
+./simavr/sim/avr_timer.c: tov_cycles_exact = (float)avr->frequency / p->ext_clock * prescaler * (top+1);
+./simavr/sim/avr_timer.c: __FUNCTION__, p->name, ((float)avr->frequency / tov_cycles_exact),
+./simavr/sim/avr_timer.c: comp_cycles = (uint32_t)((float)avr->frequency / p->ext_clock * prescaler * (ocr+1));
+./simavr/sim/avr_timer.c: avr_timer_tov(avr, avr->cycle, p);
+./simavr/sim/avr_timer.c: avr_cycle_timer_register(avr, p->tov_cycles - (avr->cycle - orig_tov_base), avr_timer_tov, p);
+./simavr/sim/avr_timer.c: //p->cs_div_value = (uint32_t)((uint64_t)avr->frequency * (1 << p->cs_div[new_cs]) / 32768);
+./simavr/sim/avr_timer.c: avr_timer_comp(p, avr->cycle, compi, 0);
+./simavr/sim/avr_timer.c: avr->data[p->r_icr] = tcnt;
+./simavr/sim/avr_timer.c: avr->data[p->r_icrh] = tcnt >> 8;
+./simavr/sim/avr_timer.c: if (new_freq <= port->avr->frequency/4) {
+./simavr/sim/avr_timer.c: if (new_freq <= port->avr->frequency/2) {
+./simavr/sim/sim_avr.c: if (!avr->time_base)
+./simavr/sim/sim_avr.c: avr->time_base = stamp;
+./simavr/sim/sim_avr.c: return stamp - avr->time_base;
+./simavr/sim/sim_avr.c: avr->flash = malloc(avr->flashend + 4);
+./simavr/sim/sim_avr.c: memset(avr->flash, 0xff, avr->flashend + 1);
+./simavr/sim/sim_avr.c: *((uint16_t*)&avr->flash[avr->flashend + 1]) = AVR_OVERFLOW_OPCODE;
+./simavr/sim/sim_avr.c: avr->codeend = avr->flashend;
+./simavr/sim/sim_avr.c: avr->data = malloc(avr->ramend + 1);
+./simavr/sim/sim_avr.c: memset(avr->data, 0, avr->ramend + 1);
+./simavr/sim/sim_avr.c: avr->trace_data = calloc(1, sizeof(struct avr_trace_data_t));
+./simavr/sim/sim_avr.c: AVR_LOG(avr, LOG_TRACE, "%s init\n", avr->mmcu);
+./simavr/sim/sim_avr.c: avr->state = cpu_Limbo;
+./simavr/sim/sim_avr.c: avr->frequency = 1000000; // can be overridden via avr_mcu_section
+./simavr/sim/sim_avr.c: if (avr->custom.init)
+./simavr/sim/sim_avr.c: avr->custom.init(avr, avr->custom.data);
+./simavr/sim/sim_avr.c: if (avr->init)
+./simavr/sim/sim_avr.c: avr->init(avr);
+./simavr/sim/sim_avr.c: avr->run = avr_callback_run_raw;
+./simavr/sim/sim_avr.c: avr->sleep = avr_callback_sleep_raw;
+./simavr/sim/sim_avr.c: avr->address_size = avr->eind ? 3 : 2;
+./simavr/sim/sim_avr.c: avr->log = 1;
+./simavr/sim/sim_avr.c: avr_regbit_set(avr, avr->reset_flags.porf); // by default set to power-on reset
+./simavr/sim/sim_avr.c: if (avr->custom.deinit)
+./simavr/sim/sim_avr.c: avr->custom.deinit(avr, avr->custom.data);
+./simavr/sim/sim_avr.c: if (avr->gdb) {
+./simavr/sim/sim_avr.c: avr->gdb = NULL;
+./simavr/sim/sim_avr.c: if (avr->vcd) {
+./simavr/sim/sim_avr.c: avr_vcd_close(avr->vcd);
+./simavr/sim/sim_avr.c: avr->vcd = NULL;
+./simavr/sim/sim_avr.c: if (avr->flash) free(avr->flash);
+./simavr/sim/sim_avr.c: if (avr->data) free(avr->data);
+./simavr/sim/sim_avr.c: if (avr->io_console_buffer.buf) {
+./simavr/sim/sim_avr.c: avr->io_console_buffer.len = 0;
+./simavr/sim/sim_avr.c: avr->io_console_buffer.size = 0;
+./simavr/sim/sim_avr.c: free(avr->io_console_buffer.buf);
+./simavr/sim/sim_avr.c: avr->io_console_buffer.buf = NULL;
+./simavr/sim/sim_avr.c: avr->flash = avr->data = NULL;
+./simavr/sim/sim_avr.c: if (avr->cycle > 0) {
+./simavr/sim/sim_avr.c: AVR_LOG(avr, LOG_OUTPUT, "%s reset (PC set to 0x%04x)\n", avr->mmcu, avr->reset_pc);
+./simavr/sim/sim_avr.c: avr->state = cpu_Running;
+./simavr/sim/sim_avr.c: for(int i = 0x20; i <= avr->ioend; i++)
+./simavr/sim/sim_avr.c: avr->data[i] = 0;
+./simavr/sim/sim_avr.c: _avr_sp_set(avr, avr->ramend);
+./simavr/sim/sim_avr.c: avr->pc = avr->reset_pc; // Likely to be zero
+./simavr/sim/sim_avr.c: avr->sreg[i] = 0;
+./simavr/sim/sim_avr.c: if (avr->reset)
+./simavr/sim/sim_avr.c: avr->reset(avr);
+./simavr/sim/sim_avr.c: avr_io_t * port = avr->io_port;
+./simavr/sim/sim_avr.c: avr->cycle = 0; // Prevent crash
+./simavr/sim/sim_avr.c: avr->state = cpu_Stopped;
+./simavr/sim/sim_avr.c: if (avr->gdb_port) {
+./simavr/sim/sim_avr.c: if (!avr->gdb)
+./simavr/sim/sim_avr.c: if (!avr->gdb)
+./simavr/sim/sim_avr.c: avr->state = cpu_Crashed;
+./simavr/sim/sim_avr.c: if (v == '\r' && avr->io_console_buffer.buf) {
+./simavr/sim/sim_avr.c: avr->io_console_buffer.buf[avr->io_console_buffer.len] = 0;
+./simavr/sim/sim_avr.c: avr->io_console_buffer.buf);
+./simavr/sim/sim_avr.c: avr->io_console_buffer.len = 0;
+./simavr/sim/sim_avr.c: if (avr->io_console_buffer.len + 1 >= avr->io_console_buffer.size) {
+./simavr/sim/sim_avr.c: avr->io_console_buffer.size += 128;
+./simavr/sim/sim_avr.c: avr->io_console_buffer.buf = (char*)realloc(
+./simavr/sim/sim_avr.c: avr->io_console_buffer.buf,
+./simavr/sim/sim_avr.c: avr->io_console_buffer.size);
+./simavr/sim/sim_avr.c: avr->io_console_buffer.buf[avr->io_console_buffer.len++] = v;
+./simavr/sim/sim_avr.c: if ((address + size) > avr->flashend+1) {
+./simavr/sim/sim_avr.c: size, avr->flashend + 1);
+./simavr/sim/sim_avr.c: memcpy(avr->flash + address, code, size);
+./simavr/sim/sim_avr.c: avr->sleep_usec += avr_cycles_to_usec(avr, howLong);
+./simavr/sim/sim_avr.c: uint32_t usec = avr->sleep_usec;
+./simavr/sim/sim_avr.c: avr->sleep_usec = 0;
+./simavr/sim/sim_avr.c: avr_gdb_processor(avr, avr->state == cpu_Stopped ? 50000 : 0);
+./simavr/sim/sim_avr.c: if (avr->state == cpu_Stopped)
+./simavr/sim/sim_avr.c: int step = avr->state == cpu_Step;
+./simavr/sim/sim_avr.c: avr->state = cpu_Running;
+./simavr/sim/sim_avr.c: avr_flashaddr_t new_pc = avr->pc;
+./simavr/sim/sim_avr.c: if (avr->state == cpu_Running) {
+./simavr/sim/sim_avr.c: avr->pc = new_pc;
+./simavr/sim/sim_avr.c: if (avr->state == cpu_Sleeping) {
+./simavr/sim/sim_avr.c: if (!avr->sreg[S_I]) {
+./simavr/sim/sim_avr.c: if (avr->log)
+./simavr/sim/sim_avr.c: avr->state = cpu_Done;
+./simavr/sim/sim_avr.c: avr->sleep(avr, sleep);
+./simavr/sim/sim_avr.c: avr->cycle += 1 + sleep;
+./simavr/sim/sim_avr.c: if (avr->state == cpu_Running || avr->state == cpu_Sleeping)
+./simavr/sim/sim_avr.c: avr->state = cpu_StepDone;
+./simavr/sim/sim_avr.c: uint64_t deadline_ns = avr_cycles_to_nsec(avr, avr->cycle + how_long);
+./simavr/sim/sim_avr.c: avr_flashaddr_t new_pc = avr->pc;
+./simavr/sim/sim_avr.c: if (avr->state == cpu_Running) {
+./simavr/sim/sim_avr.c: avr->pc = new_pc;
+./simavr/sim/sim_avr.c: if (avr->state == cpu_Sleeping) {
+./simavr/sim/sim_avr.c: if (!avr->sreg[S_I]) {
+./simavr/sim/sim_avr.c: if (avr->log)
+./simavr/sim/sim_avr.c: avr->state = cpu_Done;
+./simavr/sim/sim_avr.c: avr->sleep(avr, sleep);
+./simavr/sim/sim_avr.c: avr->cycle += 1 + sleep;
+./simavr/sim/sim_avr.c: if (avr->state == cpu_Running || avr->state == cpu_Sleeping) {
+./simavr/sim/sim_avr.c: if (avr->interrupt_state)
+./simavr/sim/sim_avr.c: avr->run(avr);
+./simavr/sim/sim_avr.c: return avr->state;
+./simavr/sim/sim_avr.c: avr->mmcu, avr->flashend, avr->ramend, avr->e2end);
+./simavr/sim/sim_avr.c: if (!avr || avr->log >= level) {
+./simavr/sim/sim_vcd_file.c: avr->state = cpu_Done;
+./simavr/sim/sim_vcd_file.c: next = (log.when * avr->frequency) / (1000*1000*1000);
+./simavr/sim/sim_vcd_file.c: when = (vcd->period * vcd->avr->frequency) /
+./simavr/sim/sim_vcd_file.c: .when = vcd->avr->cycle,
+./simavr/sim/sim_vcd_file.c: avr_init_irq(&vcd->avr->irq_pool, &s->irq, index, 1, names);
+./simavr/sim/sim_vcd_file.c: vcd->start = vcd->avr->cycle;
+./simavr/sim/avr_extint.c: if (avr->sreg[S_I]) {
+./simavr/sim/avr_extint.c: avr_io_t * periferal = avr->io_port;
+./simavr/sim/avr_extint.c: if (avr->sreg[S_I]) {
+./simavr/sim/sim_elf.c: avr->frequency = firmware->frequency;
+./simavr/sim/sim_elf.c: avr->vcc = firmware->vcc;
+./simavr/sim/sim_elf.c: avr->avcc = firmware->avcc;
+./simavr/sim/sim_elf.c: avr->aref = firmware->aref;
+./simavr/sim/sim_elf.c: avr->trace_data->codeline = malloc(scount * sizeof(avr_symbol_t*));
+./simavr/sim/sim_elf.c: memset(avr->trace_data->codeline, 0, scount * sizeof(avr_symbol_t*));
+./simavr/sim/sim_elf.c: avr->trace_data->codeline[firmware->symbol[i]->addr >> 1] =
+./simavr/sim/sim_elf.c: if (!avr->trace_data->codeline[i])
+./simavr/sim/sim_elf.c: avr->trace_data->codeline[i] = last;
+./simavr/sim/sim_elf.c: last = avr->trace_data->codeline[i];
+./simavr/sim/sim_elf.c: avr->codeend = firmware->flashsize +
+./simavr/sim/sim_elf.c: memcpy(avr->fuse, firmware->fuse, firmware->fusesize);
+./simavr/sim/sim_elf.c: if (avr->init_fuse_lock) {
+./simavr/sim/sim_elf.c: avr->init_fuse_lock(avr);
+./simavr/sim/sim_elf.c: avr->lockbits = firmware->lockbits[0];
+./simavr/sim/sim_elf.c: avr->vcd = malloc(sizeof(*avr->vcd));
+./simavr/sim/sim_elf.c: memset(avr->vcd, 0, sizeof(*avr->vcd));
+./simavr/sim/sim_elf.c: avr->vcd,
+./simavr/sim/sim_elf.c: avr->vcd->filename);
+./simavr/sim/sim_elf.c: avr_vcd_add_signal(avr->vcd, irq, 1,
+./simavr/sim/sim_elf.c: avr_vcd_add_signal(avr->vcd,
+./simavr/sim/sim_elf.c: avr_vcd_add_signal(avr->vcd, all, 8,
+./simavr/sim/sim_elf.c: avr_vcd_add_signal(avr->vcd,
+./simavr/sim/sim_elf.c: avr_vcd_add_signal(avr->vcd, bit, 1, comp);
+./simavr/sim/sim_elf.c: avr_vcd_start(avr->vcd);
+./simavr/sim/sim_elf.c: firmware->flashsize = avr->flashend + 1;
+./simavr/sim/sim_elf.c: // avr->frequency = f_cpu;
+./simavr/sim/avr_watchdog.c: p->reset_context.avr_run = avr->run;
+./simavr/sim/avr_watchdog.c: avr->run = avr_watchdog_run_callback_software_reset;
+./simavr/sim/avr_watchdog.c: p->cycle_count = (p->cycle_count * avr->frequency) / 128000;
+./simavr/sim/avr_watchdog.c: uint8_t old_v = avr->data[addr]; // allow gdb to see write...
+./simavr/sim/avr_watchdog.c: avr->data[addr] = old_v;
+./simavr/sim/avr_watchdog.c: avr->run = p->reset_context.avr_run;
+./simavr/sim/avr_eeprom.c: ee_addr = avr->data[p->r_eearl] | (avr->data[p->r_eearh] << 8);
+./simavr/sim/avr_eeprom.c: ee_addr = avr->data[p->r_eearl];
+./simavr/sim/avr_eeprom.c: avr->pc);
+./simavr/sim/avr_eeprom.c: // printf("eeprom write %04x <- %02x\n", addr, avr->data[p->r_eedr]);
+./simavr/sim/avr_eeprom.c: p->eeprom[ee_addr] = avr->data[p->r_eedr];
+./simavr/sim/avr_eeprom.c: avr->data[p->r_eedr] = p->eeprom[ee_addr];
+./simavr/sim/run_avr.c: avr->log = (log > LOG_TRACE ? LOG_TRACE : log);
+./simavr/sim/run_avr.c: avr->trace = trace;
+./simavr/sim/run_avr.c: avr->pc = f.flashbase;
+./simavr/sim/run_avr.c: for (int vi = 0; vi < avr->interrupts.vector_count; vi++)
+./simavr/sim/run_avr.c: if (avr->interrupts.vector[vi]->vector == trace_vectors[ti])
+./simavr/sim/run_avr.c: avr->interrupts.vector[vi]->trace = 1;
+./simavr/sim/run_avr.c: avr->gdb_port = port;
+./simavr/sim/run_avr.c: avr->state = cpu_Stopped;
+./simavr/sim/avr_lin.c: uint32_t lbrr = (avr->data[p->r_linbrrh] << 8) | avr->data[p->r_linbrrl];
+./simavr/sim/avr_lin.c: //uint32_t baud = avr->frequency / (lbt * (lbrr + 1));
+./simavr/sim/avr_lin.c: double baud = ((double)avr->frequency) / cycles_per_bit; // can be less than 1
+./simavr/sim/avr_lin.c: avr->data[p->r_linbtr] = 0x20;
+./simavr/sim/sim_cycle_timers.c: avr_cycle_timer_pool_t * pool = &avr->cycle_timers;
+./simavr/sim/sim_cycle_timers.c: avr->run_cycle_count = 1;
+./simavr/sim/sim_cycle_timers.c: avr->run_cycle_limit = 1;
+./simavr/sim/sim_cycle_timers.c: avr_cycle_count_t run_cycle_count = ((avr->run_cycle_limit >= sleep_cycle_count) ?
+./simavr/sim/sim_cycle_timers.c: sleep_cycle_count : avr->run_cycle_limit);
+./simavr/sim/sim_cycle_timers.c: avr->run_cycle_count = run_cycle_count ? run_cycle_count : 1;
+./simavr/sim/sim_cycle_timers.c: avr_cycle_timer_pool_t * pool = &avr->cycle_timers;
+./simavr/sim/sim_cycle_timers.c: if(pool->timer->when > avr->cycle) {
+./simavr/sim/sim_cycle_timers.c: sleep_cycle_count = pool->timer->when - avr->cycle;
+./simavr/sim/sim_cycle_timers.c: avr_cycle_timer_pool_t * pool = &avr->cycle_timers;
+./simavr/sim/sim_cycle_timers.c: when += avr->cycle;
+./simavr/sim/sim_cycle_timers.c: avr_cycle_timer_pool_t * pool = &avr->cycle_timers;
+./simavr/sim/sim_cycle_timers.c: avr_cycle_timer_pool_t * pool = &avr->cycle_timers;
+./simavr/sim/sim_cycle_timers.c: avr_cycle_timer_pool_t * pool = &avr->cycle_timers;
+./simavr/sim/sim_cycle_timers.c: return 1 + (t->when - avr->cycle);
+./simavr/sim/sim_cycle_timers.c: avr_cycle_timer_pool_t * pool = &avr->cycle_timers;
+./simavr/sim/sim_cycle_timers.c: if (when > avr->cycle)
+./simavr/sim/sim_cycle_timers.c: return avr_cycle_timer_return_sleep_run_cycles_limited(avr, when - avr->cycle);
+./simavr/sim/sim_cycle_timers.c: } while (when && when <= avr->cycle);
+./simavr/sim/sim_cycle_timers.c: avr_cycle_timer_insert(avr, when - avr->cycle, t->timer, t->param);
+./simavr/sim/sim_core.c: if (avr->trace) {\
+./simavr/sim/sim_core.c: if (avr->trace_data->codeline && avr->trace_data->codeline[avr->pc>>1]) {\
+./simavr/sim/sim_core.c: const char * symn = avr->trace_data->codeline[avr->pc>>1]->symbol; \
+./simavr/sim/sim_core.c: printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
+./simavr/sim/sim_core.c: printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
+./simavr/sim/sim_core.c:#define SREG() if (avr->trace && donttrace == 0) {\
+./simavr/sim/sim_core.c: printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
+./simavr/sim/sim_core.c: printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
+./simavr/sim/sim_core.c: printf("*** CYCLE %" PRI_avr_cycle_count "PC %04x\n", avr->cycle, avr->pc);
+./simavr/sim/sim_core.c: int pci = (avr->trace_data->old_pci + i) & 0xf;
+./simavr/sim/sim_core.c: avr->trace_data->old[pci].pc, avr->trace_data->codeline ? avr->trace_data->codeline[avr->trace_data->old[pci].pc>>1]->symbol : "unknown", OLD_PC_SIZE-i, avr->trace_data->old[pci].sp);
+./simavr/sim/sim_core.c: printf("Stack Ptr %04x/%04x = %d \n", _avr_sp_get(avr), avr->ramend, avr->ramend - _avr_sp_get(avr));
+./simavr/sim/sim_core.c: return(avr->flash[addr] | (avr->flash[addr + 1] << 8));
+./simavr/sim/sim_core.c: if (avr->io[io].irq) {
+./simavr/sim/sim_core.c: uint8_t v = avr->data[addr];
+./simavr/sim/sim_core.c: avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
+./simavr/sim/sim_core.c: avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
+./simavr/sim/sim_core.c: if (addr > avr->ramend) {
+./simavr/sim/sim_core.c: avr->pc, _avr_sp_get(avr), _avr_flash_read16le(avr, avr->pc), v, addr, (avr->ramend + 1), addr % (avr->ramend + 1));
+./simavr/sim/sim_core.c: addr = addr % (avr->ramend + 1);
+./simavr/sim/sim_core.c: avr->pc, _avr_sp_get(avr), _avr_flash_read16le(avr, avr->pc), addr, v);
+./simavr/sim/sim_core.c: if (avr->trace_data->stack_frame_index > 1 && addr > avr->trace_data->stack_frame[avr->trace_data->stack_frame_index-2].sp) {
+./simavr/sim/sim_core.c: avr->pc, _avr_sp_get(avr), addr, v);
+./simavr/sim/sim_core.c: if (avr->gdb) {
+./simavr/sim/sim_core.c: avr->data[addr] = v;
+./simavr/sim/sim_core.c: if (addr > avr->ramend) {
+./simavr/sim/sim_core.c: avr->pc, _avr_sp_get(avr), _avr_flash_read16le(avr, avr->pc),
+./simavr/sim/sim_core.c: addr, (avr->ramend + 1), addr % (avr->ramend + 1));
+./simavr/sim/sim_core.c: addr = addr % (avr->ramend + 1);
+./simavr/sim/sim_core.c: if (avr->gdb) {
+./simavr/sim/sim_core.c: return avr->data[addr];
+./simavr/sim/sim_core.c: avr->data[R_SREG] = v;
+./simavr/sim/sim_core.c: if (avr->io[io].w.c) {
+./simavr/sim/sim_core.c: avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
+./simavr/sim/sim_core.c: avr->data[r] = v;
+./simavr/sim/sim_core.c: if (avr->io[io].irq) {
+./simavr/sim/sim_core.c: avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
+./simavr/sim/sim_core.c: avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
+./simavr/sim/sim_core.c: avr->data[r] = v;
+./simavr/sim/sim_core.c: return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
+./simavr/sim/sim_core.c: if (addr <= avr->ioend)
+./simavr/sim/sim_core.c: READ_SREG_INTO(avr, avr->data[R_SREG]);
+./simavr/sim/sim_core.c: if (avr->io[io].r.c)
+./simavr/sim/sim_core.c: avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
+./simavr/sim/sim_core.c: if (avr->io[io].irq) {
+./simavr/sim/sim_core.c: uint8_t v = avr->data[addr];
+./simavr/sim/sim_core.c: avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
+./simavr/sim/sim_core.c: avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
+./simavr/sim/sim_core.c: for (int i = 0; i < avr->address_size; i++, addr >>= 8, sp--) {
+./simavr/sim/sim_core.c: return avr->address_size;
+./simavr/sim/sim_core.c: for (int i = 0; i < avr->address_size; i++, sp++) {
+./simavr/sim/sim_core.c: avr->pc, avr->trace_data->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), _avr_flash_read16le(avr, avr->pc));
+./simavr/sim/sim_core.c: avr->pc, _avr_sp_get(avr), _avr_flash_read16le(avr, avr->pc));
+./simavr/sim/sim_core.c: if (!avr->trace || donttrace)
+./simavr/sim/sim_core.c: if (avr->trace_data->touched[r])
+./simavr/sim/sim_core.c: printf("%s=%02x ", avr_regname(i), avr->data[i]);
+./simavr/sim/sim_core.c: const uint8_t vd = avr->data[d];
+./simavr/sim/sim_core.c: const uint8_t vd = avr->data[d], vr = avr->data[r];
+./simavr/sim/sim_core.c: const uint8_t vr = avr->data[r];
+./simavr/sim/sim_core.c: const uint8_t vh = avr->data[h];
+./simavr/sim/sim_core.c: const uint16_t vp = avr->data[p] | (avr->data[p + 1] << 8);
+./simavr/sim/sim_core.c: avr->trace_data->old[avr->trace_data->old_pci].pc = avr->pc;\
+./simavr/sim/sim_core.c: avr->trace_data->old[avr->trace_data->old_pci].sp = _avr_sp_get(avr);\
+./simavr/sim/sim_core.c: avr->trace_data->old_pci = (avr->trace_data->old_pci + 1) & (OLD_PC_SIZE-1);\
+./simavr/sim/sim_core.c: avr->trace_data->stack_frame[avr->trace_data->stack_frame_index].pc = avr->pc;\
+./simavr/sim/sim_core.c: avr->trace_data->stack_frame[avr->trace_data->stack_frame_index].sp = _avr_sp_get(avr);\
+./simavr/sim/sim_core.c: avr->trace_data->stack_frame_index++;
+./simavr/sim/sim_core.c: if (avr->trace_data->stack_frame_index > 0) \
+./simavr/sim/sim_core.c: avr->trace_data->stack_frame_index--;
+./simavr/sim/sim_core.c: avr->sreg[S_Z] = res == 0;
+./simavr/sim/sim_core.c: avr->sreg[S_N] = (res >> 7) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
+./simavr/sim/sim_core.c: avr->sreg[S_Z] = res == 0;
+./simavr/sim/sim_core.c: avr->sreg[S_N] = (res >> 15) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
+./simavr/sim/sim_core.c: avr->sreg[S_H] = (add_carry >> 3) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = (add_carry >> 7) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = (((rd & rr & ~res) | (~rd & ~rr & res)) >> 7) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_H] = (sub_carry >> 3) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = (sub_carry >> 7) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = (((rd & ~rr & ~res) | (~rd & rr & res)) >> 7) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_Z] = 0;
+./simavr/sim/sim_core.c: avr->sreg[S_N] = (res >> 7) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
+./simavr/sim/sim_core.c: avr->sreg[S_H] = (sub_carry >> 3) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = (sub_carry >> 7) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = (((rd & ~rr & ~res) | (~rd & rr & res)) >> 7) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_Z] = res == 0;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = vr & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
+./simavr/sim/sim_core.c: avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
+./simavr/sim/sim_core.c: avr->sreg[S_Z] = res == 0;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = vr & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_N] = res >> 7;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
+./simavr/sim/sim_core.c: avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
+./simavr/sim/sim_core.c: avr->sreg[S_V] = 0;
+./simavr/sim/sim_core.c: if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend || _avr_sp_get(avr) > avr->ramend) {
+./simavr/sim/sim_core.c:// avr->trace = 1;
+./simavr/sim/sim_core.c: avr->trace_data->touched[0] = avr->trace_data->touched[1] = avr->trace_data->touched[2] = 0;
+./simavr/sim/sim_core.c: if (unlikely(avr->pc >= avr->flashend)) {
+./simavr/sim/sim_core.c: uint32_t opcode = _avr_flash_read16le(avr, avr->pc);
+./simavr/sim/sim_core.c: avr_flashaddr_t new_pc = avr->pc + 2; // future "default" pc
+./simavr/sim/sim_core.c: uint8_t res = vd - vr - avr->sreg[S_C];
+./simavr/sim/sim_core.c: uint8_t res = vd - vr - avr->sreg[S_C];
+./simavr/sim/sim_core.c: STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
+./simavr/sim/sim_core.c: STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
+./simavr/sim/sim_core.c: uint16_t vr = avr->data[r] | (avr->data[r + 1] << 8);
+./simavr/sim/sim_core.c: int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
+./simavr/sim/sim_core.c: STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
+./simavr/sim/sim_core.c: avr->sreg[S_C] = (res >> 15) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_Z] = res == 0;
+./simavr/sim/sim_core.c: res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
+./simavr/sim/sim_core.c: res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
+./simavr/sim/sim_core.c: res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
+./simavr/sim/sim_core.c: res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
+./simavr/sim/sim_core.c: STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
+./simavr/sim/sim_core.c: avr->sreg[S_C] = c;
+./simavr/sim/sim_core.c: avr->sreg[S_Z] = res == 0;
+./simavr/sim/sim_core.c: STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":" not");
+./simavr/sim/sim_core.c: uint8_t res = vd + vr + avr->sreg[S_C];
+./simavr/sim/sim_core.c: STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
+./simavr/sim/sim_core.c: STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
+./simavr/sim/sim_core.c: STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
+./simavr/sim/sim_core.c: STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
+./simavr/sim/sim_core.c: uint8_t res = vh - k - avr->sreg[S_C];
+./simavr/sim/sim_core.c: uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
+./simavr/sim/sim_core.c: STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(d), avr->data[d]);
+./simavr/sim/sim_core.c: _avr_set_ram(avr, v+q, avr->data[d]);
+./simavr/sim/sim_core.c: STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(d), q, v+q, avr->data[v+q]);
+./simavr/sim/sim_core.c: uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
+./simavr/sim/sim_core.c: STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(d), avr->data[d]);
+./simavr/sim/sim_core.c: _avr_set_ram(avr, v+q, avr->data[d]);
+./simavr/sim/sim_core.c: STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(d), q, v+q, avr->data[d+q]);
+./simavr/sim/sim_core.c: if (!avr_has_pending_interrupts(avr) || !avr->sreg[S_I])
+./simavr/sim/sim_core.c: avr->state = cpu_Sleeping;
+./simavr/sim/sim_core.c: if (avr->gdb) {
+./simavr/sim/sim_core.c: avr->state = cpu_Stopped;
+./simavr/sim/sim_core.c: if (e && !avr->eind)
+./simavr/sim/sim_core.c: uint32_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
+./simavr/sim/sim_core.c: z |= avr->data[avr->eind] << 16;
+./simavr/sim/sim_core.c: cycle += 1 + avr->address_size;
+./simavr/sim/sim_core.c: uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
+./simavr/sim/sim_core.c: _avr_set_r(avr, 0, avr->flash[z]);
+./simavr/sim/sim_core.c: if (!avr->rampz)
+./simavr/sim/sim_core.c: uint32_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr->rampz] << 16);
+./simavr/sim/sim_core.c: _avr_set_r(avr, 0, avr->flash[z]);
+./simavr/sim/sim_core.c: STATE("lds %s[%02x], 0x%04x\n", avr_regname(d), avr->data[d], x);
+./simavr/sim/sim_core.c: uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
+./simavr/sim/sim_core.c: _avr_set_r(avr, d, avr->flash[z]);
+./simavr/sim/sim_core.c: if (!avr->rampz)
+./simavr/sim/sim_core.c: uint32_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr->rampz] << 16);
+./simavr/sim/sim_core.c: _avr_set_r(avr, d, avr->flash[z]);
+./simavr/sim/sim_core.c: _avr_set_r(avr, avr->rampz, z >> 16);
+./simavr/sim/sim_core.c: uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
+./simavr/sim/sim_core.c: uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
+./simavr/sim/sim_core.c: uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
+./simavr/sim/sim_core.c: uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
+./simavr/sim/sim_core.c: uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
+./simavr/sim/sim_core.c: uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
+./simavr/sim/sim_core.c: STATE("pop %s (@%04x)[%02x]\n", avr_regname(d), sp, avr->data[sp]);
+./simavr/sim/sim_core.c: avr->sreg[S_C] = 1;
+./simavr/sim/sim_core.c: avr->sreg[S_H] = ((res >> 3) | (vd >> 3)) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = res == 0x80;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = res != 0;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = res == 0x80;
+./simavr/sim/sim_core.c: avr->sreg[S_N] = 0;
+./simavr/sim/sim_core.c: uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vd >> 1;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = res == 0x7f;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = ((~vp & res) >> 15) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = ((~res & vp) >> 15) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_V] = ((vp & ~res) >> 15) & 1;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = ((res & ~vp) >> 15) & 1;
+./simavr/sim/sim_core.c: STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], mask, res);
+./simavr/sim/sim_core.c: STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], mask, !res?"":" not");
+./simavr/sim/sim_core.c: STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], mask, res);
+./simavr/sim/sim_core.c: STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], mask, res?"":" not");
+./simavr/sim/sim_core.c: avr->sreg[S_Z] = res == 0;
+./simavr/sim/sim_core.c: avr->sreg[S_C] = (res >> 15) & 1;
+./simavr/sim/sim_core.c: STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(d), avr->data[d]);
+./simavr/sim/sim_core.c: _avr_set_ram(avr, A, avr->data[d]);
+./simavr/sim/sim_core.c: STATE("in %s, %s[%02x]\n", avr_regname(d), avr_regname(A), avr->data[A]);
+./simavr/sim/sim_core.c: new_pc = (new_pc + o) % (avr->flashend+1);
+./simavr/sim/sim_core.c: new_pc = (new_pc + o) % (avr->flashend+1);
+./simavr/sim/sim_core.c: int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
+./simavr/sim/sim_core.c: uint8_t v = (vd & ~mask) | (avr->sreg[S_T] ? mask : 0);
+./simavr/sim/sim_core.c: avr->sreg[S_T] = (vd >> s) & 1;
+./simavr/sim/sim_core.c: avr->cycle += cycle;
+./simavr/sim/sim_core.c: if ((avr->state == cpu_Running) &&
+./simavr/sim/sim_core.c: (avr->run_cycle_count > cycle) &&
+./simavr/sim/sim_core.c: (avr->interrupt_state == 0))
+./simavr/sim/sim_core.c: avr->run_cycle_count -= cycle;
+./simavr/sim/sim_core.c: avr->pc = new_pc;
+./simavr/sim/avr_ioport.c: uint8_t ddr = avr->data[p->r_ddr];
+./simavr/sim/avr_ioport.c: uint8_t v = (avr->data[p->r_pin] & ~ddr) | (avr->data[p->r_port] & ddr);
+./simavr/sim/avr_ioport.c: avr->data[addr] = v;
+./simavr/sim/avr_ioport.c: D(if (avr->data[addr] != v) printf("** PIN%c(%02x) = %02x\r\n", p->name, addr, v);)
+./simavr/sim/avr_ioport.c: uint8_t ddr = avr->data[p->r_ddr];
+./simavr/sim/avr_ioport.c: avr_raise_irq(p->io.irq + i, (avr->data[p->r_port] >> i) & 1);
+./simavr/sim/avr_ioport.c: else if ((avr->data[p->r_port] >> i) & 1)
+./simavr/sim/avr_ioport.c: uint8_t pin = (avr->data[p->r_pin] & ~ddr) | (avr->data[p->r_port] & ddr);
+./simavr/sim/avr_ioport.c: if (avr->io[port_io].irq) {
+./simavr/sim/avr_ioport.c: avr_raise_irq(avr->io[port_io].irq + AVR_IOMEM_IRQ_ALL, avr->data[p->r_port]);
+./simavr/sim/avr_ioport.c: avr_raise_irq(avr->io[port_io].irq + i, (avr->data[p->r_port] >> i) & 1);
+./simavr/sim/avr_ioport.c: D(if (avr->data[addr] != v) printf("** PORT%c(%02x) = %02x\r\n", p->name, addr, v);)
+./simavr/sim/avr_ioport.c: avr_ioport_write(avr, p->r_port, avr->data[p->r_port] ^ v, param);
+./simavr/sim/avr_ioport.c: D(if (avr->data[addr] != v) printf("** DDR%c(%02x) = %02x\r\n", p->name, addr, v);)
+./simavr/sim/avr_ioport.c: uint8_t ddr = avr->data[p->r_ddr];
+./simavr/sim/avr_ioport.c: (avr->data[p->r_port] & ~mask) |
+./simavr/sim/avr_ioport.c: (avr->data[p->r_pin] & ~mask) |
+./simavr/sim/avr_ioport.c: int raisedata = avr->data[p->r_pcint];
+./simavr/sim/avr_ioport.c: .port = avr->data[p->r_port],
+./simavr/sim/avr_ioport.c: .ddr = avr->data[p->r_ddr],
+./simavr/sim/avr_ioport.c: .pin = avr->data[p->r_pin],
+./simavr/sim/avr_ioport.c: printf("skipping PORT%c for core %s\n", p->name, avr->mmcu);
+./simavr/sim/sim_cmds.c: avr_cmd_table_t * commands = &avr->commands;
+./simavr/sim/sim_cmds.c: avr_cmd_table_t * commands = &avr->commands;
+./simavr/sim/sim_cmds.c: avr_cmd_table_t * commands = &avr->commands;
+./simavr/sim/sim_cmds.c: if (avr->vcd)
+./simavr/sim/sim_cmds.c: avr_vcd_start(avr->vcd);
+./simavr/sim/sim_cmds.c: if (avr->vcd)
+./simavr/sim/sim_cmds.c: avr_vcd_stop(avr->vcd);
+./simavr/sim/sim_cmds.c: memset(&avr->commands, 0, sizeof(avr->commands));
+./simavr/sim/avr_flash.c: avr_flashaddr_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
+./simavr/sim/avr_flash.c: if (avr->rampz)
+./simavr/sim/avr_flash.c: z |= avr->data[avr->rampz] << 16;
+./simavr/sim/avr_flash.c: uint16_t r01 = avr->data[0] | (avr->data[1] << 8);
+./simavr/sim/avr_flash.c:// printf("AVR_IOCTL_FLASH_SPM %02x Z:%04x R01:%04x\n", avr->data[p->r_spm], z,r01);
+./simavr/sim/avr_flash.c: avr->flash[z++] = 0xff;
+./simavr/sim/avr_flash.c: avr->flash[z++] = p->tmppage[i];
+./simavr/sim/avr_flash.c: avr->flash[z++] = p->tmppage[i] >> 8;
+./simavr/sim/avr_usb.c: return p->io.avr->data[p->r_usbcon + uenum];
+./simavr/sim/avr_usb.c: avr->data[p->r_usbcon + ueint] |= 1 << ep;
+./simavr/sim/avr_usb.c: uint8_t * Rudien = &p->io.avr->data[p->r_usbcon + udien];
+./simavr/sim/avr_usb.c: uint8_t * Rudint = &p->io.avr->data[p->r_usbcon + udint];
+./simavr/sim/avr_usb.c: if(avr->data[addr]&1 && !(v&1))
+./simavr/sim/avr_usb.c: avr->data[p->r_usbcon + ueint] &= 0xff ^ (1 << ep); // mark ep0 interrupt
+./simavr/sim/avr_usb.c: if (avr->data[p->r_usbcon + udcon] & 1)
+./simavr/sim/avr_usb.c: p->io.avr->data[p->r_usbcon + i] = 0;
+./simavr/sim/avr_usb.c: p->io.avr->data[p->r_usbcon] = 0x20;
+./simavr/sim/avr_usb.c: p->io.avr->data[p->r_usbcon + udcon] = 1;
+./simavr/sim/avr_twi.c: uint16_t bitrate = p->io.avr->data[p->r_twbr];
+./simavr/sim/avr_twi.c: if (avr->data[p->r_twar]) {
+./simavr/sim/avr_twi.c: AVR_TRACE(avr, "TWEN Slave: %02x&%02x\n", avr->data[p->r_twar] >> 1, avr->data[p->r_twamr] >> 1);
+./simavr/sim/avr_twi.c: avr_twi_irq_msg(TWI_COND_READ | TWI_COND_ACK, p->peer_addr, avr->data[p->r_twdr]));
+./simavr/sim/avr_twi.c: avr_twi_irq_msg(TWI_COND_ADDR + (do_ack ? TWI_COND_ACK : 0), p->peer_addr, avr->data[p->r_twdr]));
+./simavr/sim/avr_twi.c: p->peer_addr, avr->data[p->r_twdr]));
+./simavr/sim/avr_twi.c: AVR_TRACE(avr, "I2C WRITE byte %02x to %02x\n", avr->data[p->r_twdr], p->peer_addr);
+./simavr/sim/avr_twi.c: avr_twi_irq_msg(msgv, p->peer_addr, avr->data[p->r_twdr]));
+./simavr/sim/avr_twi.c: AVR_TRACE(avr, "I2C Master address %02x\n", avr->data[p->r_twdr]);
+./simavr/sim/avr_twi.c: p->peer_addr = avr->data[p->r_twdr];
+./simavr/sim/avr_twi.c: return avr->data[p->r_twdr];
+./simavr/sim/avr_twi.c: uint8_t mask = ~avr->data[p->r_twamr] >> 1;
+./simavr/sim/avr_twi.c: msg.u.twi.addr, avr->data[p->r_twar] >> 1, mask);
+./simavr/sim/avr_twi.c: if (p->peer_addr == ((avr->data[p->r_twar] >> 1) & mask)) {
+./simavr/sim/avr_twi.c: if (avr->data[p->r_twar] & 1) {
+./simavr/sim/avr_twi.c: avr->data[p->r_twdr] = msg.u.twi.data;
+./simavr/sim/avr_twi.c: avr->data[p->r_twdr] = msg.u.twi.data;
+./simavr/sim/sim_gdb.c: avr->data[R_SPL], avr->data[R_SPH],
+./simavr/sim/sim_gdb.c: avr->pc & 0xff, (avr->pc >> 8) & 0xff,
+./simavr/sim/sim_gdb.c: (avr->pc >> 16) & 0xff);
+./simavr/sim/sim_gdb.c: g->avr->data[regi] = *src;
+./simavr/sim/sim_gdb.c: g->avr->data[R_SREG] = *src;
+./simavr/sim/sim_gdb.c: g->avr->data[R_SPL] = src[0];
+./simavr/sim/sim_gdb.c: g->avr->data[R_SPH] = src[1];
+./simavr/sim/sim_gdb.c: g->avr->pc = src[0] | (src[1] << 8) | (src[2] << 16) | (src[3] << 24);
+./simavr/sim/sim_gdb.c: sprintf(rep, "%02x", g->avr->data[regi]);
+./simavr/sim/sim_gdb.c: sprintf(rep, "%02x%02x", g->avr->data[R_SPL], g->avr->data[R_SPH]);
+./simavr/sim/sim_gdb.c: g->avr->pc & 0xff, (g->avr->pc>>8)&0xff, (g->avr->pc>>16)&0xff);
+./simavr/sim/sim_gdb.c: avr->state = cpu_Stopped;
+./simavr/sim/sim_gdb.c: avr->state = cpu_Stopped;
+./simavr/sim/sim_gdb.c: base + count + 32 > avr->ioend) {
+./simavr/sim/sim_gdb.c: if (addr + count > avr->ioend)
+./simavr/sim/sim_gdb.c: count = avr->ioend + 1 - addr;
+./simavr/sim/sim_gdb.c: name, avr->data[addr + i]);
+./simavr/sim/sim_gdb.c: avr->ioend > REG_NAME_COUNT ?
+./simavr/sim/sim_gdb.c: REG_NAME_COUNT - 32 : avr->ioend - 32;
+./simavr/sim/sim_gdb.c: if (addr < avr->flashend) {
+./simavr/sim/sim_gdb.c: src = avr->flash + addr;
+./simavr/sim/sim_gdb.c: if (addr + len > avr->flashend)
+./simavr/sim/sim_gdb.c: len = avr->flashend - addr;
+./simavr/sim/sim_gdb.c: } else if (addr < avr->flashend) {
+./simavr/sim/sim_gdb.c: src = avr->flash + addr;
+./simavr/sim/sim_gdb.c: limit = avr->flash + avr->flashend;
+./simavr/sim/sim_gdb.c: (src - avr->flash) - addr);)
+./simavr/sim/sim_gdb.c: addr = src - avr->flash; // Address of end.
+./simavr/sim/sim_gdb.c: if (addr > avr->codeend) // Checked by sim_core.c
+./simavr/sim/sim_gdb.c: avr->codeend = addr;
+./simavr/sim/sim_gdb.c: g->avr->ramend + 1, g->avr->flashend + 1);
+./simavr/sim/sim_gdb.c: if (addr <= avr->flashend) {
+./simavr/sim/sim_gdb.c: src = avr->flash + addr;
+./simavr/sim/sim_gdb.c: } else if (addr >= 0x800000 && (addr - 0x800000) <= avr->ramend) {
+./simavr/sim/sim_gdb.c: src = avr->data + addr - 0x800000;
+./simavr/sim/sim_gdb.c: } else if (addr == (0x800000 + avr->ramend + 1) && len == 2) {
+./simavr/sim/sim_gdb.c: } else if (addr >= 0x810000 && (addr - 0x810000) <= avr->e2end) {
+./simavr/sim/sim_gdb.c: addr, len, avr->ramend+1);
+./simavr/sim/sim_gdb.c: read_hex_string(start + 1, avr->flash + addr, strlen(start+1));
+./simavr/sim/sim_gdb.c: } else if (addr >= 0x800000 && (addr - 0x800000) <= avr->ramend) {
+./simavr/sim/sim_gdb.c: read_hex_string(start + 1, avr->data + addr - 0x800000, strlen(start+1));
+./simavr/sim/sim_gdb.c: } else if (addr >= 0x810000 && (addr - 0x810000) <= avr->e2end) {
+./simavr/sim/sim_gdb.c: avr->state = cpu_Running;
+./simavr/sim/sim_gdb.c: avr->state = cpu_Step;
+./simavr/sim/sim_gdb.c: avr->state = cpu_Stopped;
+./simavr/sim/sim_gdb.c: if (addr > avr->flashend ||
+./simavr/sim/sim_gdb.c: if (addr > avr->ramend ||
+./simavr/sim/sim_gdb.c: if (avr->state = cpu_Stopped)
+./simavr/sim/sim_gdb.c: avr->state = cpu_Running;
+./simavr/sim/sim_gdb.c: avr->state = cpu_Done;
+./simavr/sim/sim_gdb.c: g->avr->state = cpu_Stopped;
+./simavr/sim/sim_gdb.c: g->avr->state = cpu_Running; // resume
+./simavr/sim/sim_gdb.c: g->avr->state = cpu_Stopped;
+./simavr/sim/sim_gdb.c: avr_gdb_t *g = avr->gdb;
+./simavr/sim/sim_gdb.c: avr_gdb_t *g = avr->gdb;
+./simavr/sim/sim_gdb.c: avr->state = cpu_Stopped;
+./simavr/sim/sim_gdb.c: if (!avr || !avr->gdb)
+./simavr/sim/sim_gdb.c: avr_gdb_t * g = avr->gdb;
+./simavr/sim/sim_gdb.c: if (avr->state == cpu_Running &&
+./simavr/sim/sim_gdb.c: gdb_watch_find(&g->breakpoints, avr->pc) != -1) {
+./simavr/sim/sim_gdb.c: DBG(printf("avr_gdb_processor hit breakpoint at %08x\n", avr->pc);)
+./simavr/sim/sim_gdb.c: avr->state = cpu_Stopped;
+./simavr/sim/sim_gdb.c: } else if (avr->state == cpu_StepDone) {
+./simavr/sim/sim_gdb.c: avr->state = cpu_Stopped;
+./simavr/sim/sim_gdb.c: if (avr->gdb)
+./simavr/sim/sim_gdb.c: avr->gdb = NULL;
+./simavr/sim/sim_gdb.c: address.sin_port = htons (avr->gdb_port);
+./simavr/sim/sim_gdb.c: printf("avr_gdb_init listening on port %d\n", avr->gdb_port);
+./simavr/sim/sim_gdb.c: avr->gdb = g;
+./simavr/sim/sim_gdb.c: avr->run = avr_callback_run_gdb;
+./simavr/sim/sim_gdb.c: avr->sleep = avr_callback_sleep_gdb;
+./simavr/sim/sim_gdb.c: if (!avr->gdb)
+./simavr/sim/sim_gdb.c: avr->run = avr_callback_run_raw; // restore normal callbacks
+./simavr/sim/sim_gdb.c: avr->sleep = avr_callback_sleep_raw;
+./simavr/sim/sim_gdb.c: if (avr->gdb->listen != -1)
+./simavr/sim/sim_gdb.c: close(avr->gdb->listen);
+./simavr/sim/sim_gdb.c: avr->gdb->listen = -1;
+./simavr/sim/sim_gdb.c: if (avr->gdb->s != -1)
+./simavr/sim/sim_gdb.c: close(avr->gdb->s);
+./simavr/sim/sim_gdb.c: avr->gdb->s = -1;
+./simavr/sim/sim_gdb.c: free(avr->gdb);
+./simavr/sim/sim_gdb.c: avr->gdb = NULL;
+./simavr/sim/avr_spi.c: avr_raise_irq(p->io.irq + SPI_IRQ_OUTPUT, avr->data[p->r_spdr]);
+./simavr/sim/avr_spi.c: uint16_t clock_shift = _avr_spi_clkdiv[avr->data[p->r_spcr]&0b11];
+./simavr/sim/avr_spi.c: avr_raise_irq(p->io.irq + SPI_IRQ_OUTPUT, avr->data[p->r_spdr]);
+./tests/test_atmega2560_uart_echo.c: avr->log = LOG_TRACE;
+./tests/tests.c: if (avr->state == cpu_Stopped)
+./tests/tests.c: return avr->state;
+./tests/tests.c: uint16_t new_pc = avr->pc;
+./tests/tests.c: if (avr->state == cpu_Running)
+./tests/tests.c: avr->pc = new_pc;
+./tests/tests.c: if (avr->state == cpu_Sleeping) {
+./tests/tests.c: if (!avr->sreg[S_I]) {
+./tests/tests.c: avr->cycle += 1 + sleep;
+./tests/tests.c: if (avr->state == cpu_Running || avr->state == cpu_Sleeping)
+./tests/tests.c: return avr->state;
+./tests/tests.c: avr->custom.deinit = special_deinit_longjmp_cb;
+./tests/tests.c: tests_cycle_count = avr->cycle;
+./tests/atmega88_uart_echo.c: // see http://www.nongnu.org/avr-libc/user-manual/group__util__setbaud.html
+./tests/atmega2560_uart_echo.c:#ifdef USART3_RX_vect_num // stupid ubuntu has antique avr-libc
+./tests/atmega2560_uart_echo.c: // see http://www.nongnu.org/avr-libc/user-manual/group__util__setbaud.html
+./examples/board_i2ctest/i2ctest.c: avr->gdb_port = 1234;
+./examples/board_i2ctest/i2ctest.c: //avr->state = cpu_Stopped;
+./examples/board_rotenc/rotenc_test.c: //avr->gdb_port = 1234;
+./examples/board_rotenc/rotenc_test.c: //avr->state = cpu_Stopped;
+./examples/board_ledramp/ledramp.c: avr->gdb_port = 1234;
+./examples/board_ledramp/ledramp.c: //avr->state = cpu_Stopped;
+./examples/simuc/src/simavr/parts/uart_pty.c: p->irq = avr_alloc_irq(&avr->irq_pool, 0, IRQ_UART_PTY_COUNT, irq_names);
+./examples/simuc/src/simavr/parts/uart_pty.c: snprintf(link, sizeof(link), "/tmp/simavr-uart%c%s", uart, ti == 1 ? "-tap" : "");
+./examples/board_ds1338/twimaster.c:* Software: AVR-GCC 3.4.3 / avr-libc 1.2.3\r
+./examples/board_ds1338/ds1338demo.c: avr->gdb_port = 1234;
+./examples/board_ds1338/ds1338demo.c: avr->state = cpu_Stopped;
+./examples/shared/twimaster.c:* Software: AVR-GCC 3.4.3 / avr-libc 1.2.3\r
+./examples/parts/uart_pty.c: p->irq = avr_alloc_irq(&avr->irq_pool, 0, IRQ_UART_PTY_COUNT, irq_names);
+./examples/parts/uart_pty.c: snprintf(link, sizeof(link), "/tmp/simavr-uart%c%s", uart, ti == 1 ? "-tap" : "");
+./examples/parts/i2c_eeprom.c: p->irq = avr_alloc_irq(&avr->irq_pool, 0, 2, _ee_irq_names);
+./examples/parts/ac_input.c: b->irq = avr_alloc_irq(&avr->irq_pool, 0, IRQ_AC_COUNT, &name);
+./examples/parts/ds1338_virt.c: p->irq = avr_alloc_irq(&avr->irq_pool, 0, DS1338_IRQ_COUNT, _ds1338_irq_names);
+./examples/parts/hd44780.c: b->irq = avr_alloc_irq(&avr->irq_pool, 0, IRQ_HD44780_COUNT, irq_names);
+./examples/parts/hc595.c: p->irq = avr_alloc_irq(&avr->irq_pool, 0, IRQ_HC595_COUNT, irq_names);
+./examples/parts/button.c: b->irq = avr_alloc_irq(&avr->irq_pool, 0, IRQ_BUTTON_COUNT, &name);
+./examples/parts/rotenc.c: &avr->irq_pool,
+./examples/parts/ssd1306_virt.c: part->irq = avr_alloc_irq (&avr->irq_pool, 0, IRQ_SSD1306_COUNT,
+./examples/parts/uart_udp.c: p->irq = avr_alloc_irq(&avr->irq_pool, 0, IRQ_UART_UDP_COUNT, irq_names);
+./examples/board_timer_64led/timer_64led.c: avr->gdb_port = 1234;
+./examples/board_timer_64led/timer_64led.c: //avr->state = cpu_Stopped;
+./examples/board_simduino/simduino.c: (void)ftruncate(flash_data->avr_flash_fd, avr->flashend + 1);
+./examples/board_simduino/simduino.c: ssize_t r = read(flash_data->avr_flash_fd, avr->flash, avr->flashend + 1);
+./examples/board_simduino/simduino.c: if (r != avr->flashend + 1) {
+./examples/board_simduino/simduino.c: ssize_t r = write(flash_data->avr_flash_fd, avr->flash, avr->flashend + 1);
+./examples/board_simduino/simduino.c: if (r != avr->flashend + 1) {
+./examples/board_simduino/simduino.c: avr->custom.init = avr_special_init;
+./examples/board_simduino/simduino.c: avr->custom.deinit = avr_special_deinit;
+./examples/board_simduino/simduino.c: avr->custom.data = &flash_data;
+./examples/board_simduino/simduino.c: avr->frequency = freq;
+./examples/board_simduino/simduino.c: memcpy(avr->flash + boot_base, boot, boot_size);
+./examples/board_simduino/simduino.c: avr->pc = boot_base;
+./examples/board_simduino/simduino.c: avr->codeend = avr->flashend;
+./examples/board_simduino/simduino.c: avr->log = 1 + verbose;
+./examples/board_simduino/simduino.c: avr->gdb_port = 1234;
+./examples/board_simduino/simduino.c: avr->state = cpu_Stopped;
+./examples/extra_board_usb/simusb.c: if(avr->flash) free(avr->flash);
+./examples/extra_board_usb/simusb.c: (void)ftruncate(flash_data->avr_flash_fd, avr->flashend + 1);
+./examples/extra_board_usb/simusb.c: avr->flash = (uint8_t*)mmap(NULL, avr->flashend + 1, // 32k is multiple of 4096
+./examples/extra_board_usb/simusb.c: if (!avr->flash) {
+./examples/extra_board_usb/simusb.c: munmap( avr->flash, avr->flashend + 1);
+./examples/extra_board_usb/simusb.c: avr->flash = NULL;
+./examples/extra_board_usb/simusb.c: avr->custom.init = avr_special_init;
+./examples/extra_board_usb/simusb.c: avr->custom.deinit = avr_special_deinit;
+./examples/extra_board_usb/simusb.c: avr->custom.data = &flash_data;
+./examples/extra_board_usb/simusb.c: //avr->reset = NULL;
+./examples/extra_board_usb/simusb.c: avr->frequency = 8000000;
+./examples/extra_board_usb/simusb.c: memcpy(avr->flash + base, boot, size);
+./examples/extra_board_usb/simusb.c: avr->pc = base;
+./examples/extra_board_usb/simusb.c: avr->codeend = avr->flashend;
+./examples/extra_board_usb/simusb.c: avr->gdb_port = 1234;
+./examples/extra_board_usb/simusb.c: //avr->state = cpu_Stopped;
projects / sx / simavr.git / commitdiff