// made to trigger potential watchpoints
v = avr_core_watch_read(avr, addr);
- // should always trigger that timer
-// if (!uart_fifo_isempty(&p->input))
- avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p);
+ // trigger timer if more characters are pending
+ if (!uart_fifo_isempty(&p->input))
+ avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p);
return v;
}
if (addr == p->r_udr) {
avr_core_watch_write(avr, addr, v);
- avr_regbit_clear(avr, p->udrc.raised);
+ if ( p->udrc.vector)
+ avr_regbit_clear(avr, p->udrc.raised);
avr_cycle_timer_register_usec(avr,
p->usec_per_byte, avr_uart_txc_raise, p); // should be uart speed dependent
if (avr_regbit_get(avr, p->txen))
avr_raise_irq(p->io.irq + UART_IRQ_OUTPUT, v);
}
- if (addr == p->udrc.enable.reg) {
+ if (p->udrc.vector && addr == p->udrc.enable.reg) {
/*
* If enabling the UDRC interrupt, raise it immediately if FIFO is empty
*/
avr_raise_interrupt(avr, &p->udrc);
}
}
- if (addr == p->udrc.raised.reg) {
+ if (p->udrc.vector && addr == p->udrc.raised.reg) {
// get the bits before the write
//uint8_t udre = avr_regbit_get(avr, p->udrc.raised);
uint8_t txc = avr_regbit_get(avr, p->txc.raised);
{
avr_uart_t * p = (avr_uart_t *)io;
avr_t * avr = p->io.avr;
- avr_regbit_set(avr, p->udrc.raised);
+ if (p->udrc.vector)
+ avr_regbit_set(avr, p->udrc.raised);
avr_irq_register_notify(p->io.irq + UART_IRQ_INPUT, avr_uart_irq_input, p);
avr_cycle_timer_cancel(avr, avr_uart_rxc_raise, p);
avr_cycle_timer_cancel(avr, avr_uart_txc_raise, p);
p->io.irq[UART_IRQ_OUT_XON].flags |= IRQ_FLAG_FILTERED;
avr_register_io_write(avr, p->r_udr, avr_uart_write, p);
- avr_register_io_write(avr, p->udrc.enable.reg, avr_uart_write, p);
avr_register_io_read(avr, p->r_udr, avr_uart_read, p);
// monitor code that reads the rxc flag, and delay it a bit
avr_register_io_read(avr, p->rxc.raised.reg, avr_uart_rxc_read, p);
- avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);
- avr_register_io_write(avr, p->r_ubrrl, avr_uart_baud_write, p);
+ if (p->udrc.vector)
+ avr_register_io_write(avr, p->udrc.enable.reg, avr_uart_write, p);
+ if (p->r_ucsra)
+ avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);
+ if (p->r_ubrrl)
+ avr_register_io_write(avr, p->r_ubrrl, avr_uart_baud_write, p);
}