376af03b1deb99615632f42065f73ad80b211cd0

diff --git a/simavr/cores/sim_megax.h b/simavr/cores/sim_megax.h
index b125cfc513144401179f57e16bc77f5c9d4dee97..7d4379dd19da034b4160f31988fa2f5588155799 100644 (file)
--- a/simavr/cores/sim_megax.h
+++ b/simavr/cores/sim_megax.h
@@ -172,8 +172,11 @@ const struct mcu_t SIM_CORENAME = {
        },
        .timer0 = {
                .name = '0',
+               .wgm_op = {
+                       [0] = AVR_TIMER_WGM_NORMAL8(),
+                       // CTC etc. are missing because atmega8 does not support them on timer0
+               },
                .cs = { AVR_IO_REGBIT(TCCR0, CS00), AVR_IO_REGBIT(TCCR0, CS01), AVR_IO_REGBIT(TCCR0, CS02) },
-               //              .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
                .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */},
 
                .r_tcnt = TCNT0,
@@ -183,6 +186,7 @@ const struct mcu_t SIM_CORENAME = {
                        .raised = AVR_IO_REGBIT(TIFR, TOV0),
                        .vector = TIMER0_OVF_vect,
                },
+               // Compare Output Mode is missing for timer0 as atmega8 does not support it
        },
        .timer1 = {
                .name = '1',