382900645b1f7244d1b29cc851314c3e194c84e3

specification for muls insruction states 2 cycles, not one as implimented.

bug find credit goes to: Shay Green <gblargg@gmail.com>

	modified:   sim_core.c

diff --git a/simavr/sim/sim_core.c b/simavr/sim/sim_core.c
index 03d46ffd6fe83e512a56451ecbf15a321897d419..a30cefe0b70cf4634b49823ae87a29383628e2df 100644 (file)
--- a/simavr/sim/sim_core.c
+++ b/simavr/sim/sim_core.c
@@ -538,6 +538,7 @@ avr_flashaddr_t avr_run_one(avr_t * avr)
                                                                        _avr_set_r(avr, 1, res >> 8);
                                                                        avr->sreg[S_C] = (res >> 15) & 1;
                                                                        avr->sreg[S_Z] = res == 0;
+                                                                       cycle++;
                                                                        SREG();
                                                                }       break;
                                                                case 0x0300: {  // MUL Multiply 0000 0011 fddd frrr