.vector = PCINT1_vect,
},
.r_pcint = PCMSK1,
- .mask = 1, // PE0 has PCINT8
- .shift = 0
+ .mask = 1, // PE0 has PCINT8
+ .shift = 0
},
AVR_IOPORT_DECLARE(f, 'F', F),
AVR_IOPORT_DECLARE(g, 'G', G),
.vector = PCINT1_vect,
},
.r_pcint = PCMSK1,
- .mask = 0b11111110, // PJ0-6 have PCINT9-15
- .shift = -1
+ .mask = 0b11111110, // PJ0-6 have PCINT9-15
+ .shift = -1
},
AVR_IOPORT_DECLARE_PC(k, 'K', K, 2), // PK0-7 have PCINT16-23
AVR_IOPORT_DECLARE(l, 'L', L),
.vector = TIMER2_COMPA_vect,
},
},
- // TIMER2_COMPB is only appeared in 1280
+ // TIMER2_COMPB is only appeared in 1280
//[AVR_TIMER_COMPB] = {
// .r_ocr = OCR2B,
// .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
}
avr_kind_t mega1280 = {
- .names = { "atmega1280" },
- .make = make
+ .names = { "atmega1280" },
+ .make = make
};
void m1280_init(struct avr_t * avr)
avr_extint_poll_context_t *poll = (avr_extint_poll_context_t *)param;
avr_extint_t * p = poll->extint;
- /* Check for change of interrupt mode. */
+ /* Check for change of interrupt mode. */
- if (avr_regbit_get_array(avr, p->eint[poll->eint_no].isc, 2))
+ if (avr_regbit_get_array(avr, p->eint[poll->eint_no].isc, 2))
goto terminate_poll;
- char port = p->eint[poll->eint_no].port_ioctl & 0xFF;
+ uint8_t port = p->eint[poll->eint_no].port_ioctl & 0xFF;
avr_ioport_state_t iostate;
if (avr_ioctl(avr, AVR_IOCTL_IOPORT_GETSTATE( port ), &iostate) < 0)
goto terminate_poll;
for (int i = 0; i < EXTINT_COUNT; i++) {
if (p->eint[i].port_ioctl) {
- avr_irq_register_notify(p->io.irq + i, avr_extint_irq_notify, p);
+ avr_irq_register_notify(p->io.irq + i, avr_extint_irq_notify, p);
if (p->eint[i].isc[1].reg) // level triggering available
p->eint[i].strict_lvl_trig = 1; // turn on repetitive level triggering by default
avr_register_io(avr, &p->io);
for (int i = 0; i < EXTINT_COUNT; i++) {
- if (!p->eint[i].port_ioctl)
- break;
+ if (!p->eint[i].port_ioctl)
+ break;
avr_register_vector(avr, &p->eint[i].vector);
- }
+ }
// allocate this module's IRQ
avr_io_setirqs(&p->io, AVR_IOCTL_EXTINT_GETIRQ(), EXTINT_COUNT, NULL);