81b78e08b96c795fa8bce83523526c6b09f822b5

cores: Adds missing external interrupt for m16/m32

diff --cc simavr/cores/sim_megax.h
index c908e8ed1d855f343451c9e8f5122c867b72618a,0f650855cb9894beea6d49de39a0a9d490b1a6d3..ceda0427023460bdbf63a78914816c55a0972dab
--- 1/simavr/cores/sim_megax.h
--- 2/simavr/cores/sim_megax.h
+++ b/simavr/cores/sim_megax.h
@@@ -88,13 -88,24 +88,16 @@@ const struct mcu_t SIM_CORENAME = 
        .extint = {
                AVR_EXTINT_DECLARE(0, 'D', PD2),
                AVR_EXTINT_DECLARE(1, 'D', PD3),
+ #ifdef INT2
+               AVR_ASYNC_EXTINT_DECLARE(2, 'B', PB2),
+ #endif
        },
  #ifdef PORTA
 -      .porta = {
 -              .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
 -      },
 +      AVR_IOPORT_DECLARE(a, 'A', A),
  #endif
 -      .portb = {
 -              .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
 -      },
 -      .portc = {
 -              .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
 -      },
 -      .portd = {
 -              .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
 -      },
 +      AVR_IOPORT_DECLARE(b, 'B', B),
 +      AVR_IOPORT_DECLARE(c, 'C', C),
 +      AVR_IOPORT_DECLARE(d, 'D', D),
        .uart = {
           // no PRUSART .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
                .name = '0',