8a362b7623ed36cb04b06fbe893e31dbc90f55ef

diff --git a/simavr/cores/sim_mega128.c b/simavr/cores/sim_mega128.c
index ce142a55ff4a7e40725fe763008bc2e4063d4f6d..8d725d38cd155890e813f16b75cbcb168cafb3df 100644 (file)
--- a/simavr/cores/sim_mega128.c
+++ b/simavr/cores/sim_mega128.c
@@ -473,6 +473,7 @@ const struct mcu_t {
                .twi = {
                        .enable = AVR_IO_REGBIT(TWCR, TWIE),
                        .raised = AVR_IO_REGBIT(TWCR, TWINT),
+                       .raise_sticky = 1,
                        .vector = TWI_vect,
                },
        },

diff --git a/simavr/cores/sim_mega1280.c b/simavr/cores/sim_mega1280.c
index 6f4999d26f4143d26311f52222853487c9284d68..165a0543f336d85737cc7da7a6498743e2ba9117 100755 (executable)
--- a/simavr/cores/sim_mega1280.c
+++ b/simavr/cores/sim_mega1280.c
@@ -602,6 +602,7 @@ const struct mcu_t {
                .twi = {
                        .enable = AVR_IO_REGBIT(TWCR, TWIE),
                        .raised = AVR_IO_REGBIT(TWCR, TWINT),
+                       .raise_sticky = 1,
                        .vector = TWI_vect,
                },
        },

diff --git a/simavr/cores/sim_mega1281.c b/simavr/cores/sim_mega1281.c
index 8ec486c04ac83a7957ab7c99d315c2465f4bf7d6..bf81eb2c1b5287c88ea42fff199fafd6c992e251 100644 (file)
--- a/simavr/cores/sim_mega1281.c
+++ b/simavr/cores/sim_mega1281.c
@@ -501,6 +501,7 @@ const struct mcu_t {
                .twi = {
                        .enable = AVR_IO_REGBIT(TWCR, TWIE),
                        .raised = AVR_IO_REGBIT(TWCR, TWINT),
+                       .raise_sticky = 1,
                        .vector = TWI_vect,
                },
        },

diff --git a/simavr/cores/sim_megax.h b/simavr/cores/sim_megax.h
index 65f5616a9e0c50b16aa36cfe1ed6980149aa4043..b80469dad39abe4db61d1bc501c3aa73d99bdb62 100644 (file)
--- a/simavr/cores/sim_megax.h
+++ b/simavr/cores/sim_megax.h
@@ -314,6 +314,7 @@ const struct mcu_t SIM_CORENAME = {
                .twi = {
                        .enable = AVR_IO_REGBIT(TWCR, TWIE),
                        .raised = AVR_IO_REGBIT(TWCR, TWINT),
+                       .raise_sticky = 1,
                        .vector = TWI_vect,
                },
        },

diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index 030aebba00eb276a8a26ff22ef2e1f4b47b07ac3..4b6c463410a51ef2d796d416a1adddc727c00d38 100644 (file)
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -418,6 +418,7 @@ const struct mcu_t SIM_CORENAME = {
                .twi = {
                        .enable = AVR_IO_REGBIT(TWCR, TWIE),
                        .raised = AVR_IO_REGBIT(TWCR, TWINT),
+                       .raise_sticky = 1,
                        .vector = TWI_vect,
                },
        },

diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index 385bc8f20ad101ead1a5d0a71d96d0cac811f324..51f2d24285295dd0d5414cf019fa34924f241c35 100644 (file)
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -364,6 +364,7 @@ const struct mcu_t SIM_CORENAME = {
                .twi = {
                        .enable = AVR_IO_REGBIT(TWCR, TWIE),
                        .raised = AVR_IO_REGBIT(TWCR, TWINT),
+                       .raise_sticky = 1,
                        .vector = TWI_vect,
                },
        },