8e02e6fc02136472f4bad8415a6005438258daa5

diff --git a/simavr/cores/sim_mega16.c b/simavr/cores/sim_mega16.c
index bf2ecb1c17a0cfd036f68153f0f2e121ebfba015..2bd092db833143f5ec2c5509f78f1b64d2ecf174 100644 (file)
--- a/simavr/cores/sim_mega16.c
+++ b/simavr/cores/sim_mega16.c
@@ -27,6 +27,9 @@
 #define SIM_MMCU               "atmega16"
 #define SIM_CORENAME   mcu_mega16
 
+#define ICP_PORT       PORTD
+#define ICP_PIN                6
+       
 #define _AVR_IO_H_
 #define __ASSEMBLER__
 #include "avr/iom16.h"

diff --git a/simavr/cores/sim_mega32.c b/simavr/cores/sim_mega32.c
index 40b74b433cae88758aa61d3da23f5ae05803aff9..4c5bc0514be9fc6991587bbcbdba8c489cdc72cb 100644 (file)
--- a/simavr/cores/sim_mega32.c
+++ b/simavr/cores/sim_mega32.c
@@ -27,6 +27,9 @@
 #define SIM_MMCU               "atmega32"
 #define SIM_CORENAME   mcu_mega32
 
+#define ICP_PORT       PORTD
+#define ICP_PIN                6
+
 #define _AVR_IO_H_
 #define __ASSEMBLER__
 #include "avr/iom32.h"

diff --git a/simavr/cores/sim_mega8.c b/simavr/cores/sim_mega8.c
index 74acf983556b49007cfa7202c429323c908beaa5..01c177dd5d6b2463374abdf11a894d0e43fc8255 100644 (file)
--- a/simavr/cores/sim_mega8.c
+++ b/simavr/cores/sim_mega8.c
@@ -25,6 +25,9 @@
 #define SIM_MMCU               "atmega8"
 #define SIM_CORENAME   mcu_mega8
 
+#define ICP_PORT       PORTB
+#define ICP_PIN                0
+
 #define _AVR_IO_H_
 #define __ASSEMBLER__
 #include "avr/iom8.h"

diff --git a/simavr/cores/sim_megax.h b/simavr/cores/sim_megax.h
index 1cfaa078b0ba3ee8ecb641f9cf80a78d6d14d358..b125cfc513144401179f57e16bc77f5c9d4dee97 100644 (file)
--- a/simavr/cores/sim_megax.h
+++ b/simavr/cores/sim_megax.h
@@ -211,7 +211,7 @@ const struct mcu_t SIM_CORENAME = {
                .r_tcnth = TCNT1H,
 
                .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
-               .icp = AVR_IO_REGBIT(PORTD, 4),
+               .icp = AVR_IO_REGBIT(ICP_PORT, ICP_PIN),
 
                .overflow = {
                        .enable = AVR_IO_REGBIT(TIMSK, TOIE1),