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Commit 95eb3ec2fe34f10e7b8b58a2f5f367fcf02bb926
authorMichel Pollet <github.com@pollet.net>
Thu, 1 Apr 2021 18:28:53 +0000 (19:28 +0100)
committerGitHub <noreply@github.com>
Thu, 1 Apr 2021 18:28:53 +0000 (19:28 +0100)
Implement the BIN and IPR bits for attinyX5 and change the ADC sample timing …


Trivial merge
simulation of megaAvr microcontrollers