9e52a7ecd4a00a02debd75184ff9daa8d170ac39

Updated the cores that have UART(s) with extra flags.

Signed-off-by: Michel Pollet <buserror@gmail.com>

diff --git a/simavr/cores/sim_mega128.c b/simavr/cores/sim_mega128.c
index 6d4e1d875ad4be09bd5313d7e32f2c610a52d9a7..460a66bc3525ac2d13fbe5e0cb10284a173f8d9d 100644 (file)
--- a/simavr/cores/sim_mega128.c
+++ b/simavr/cores/sim_mega128.c
@@ -107,6 +107,8 @@ struct mcu_t {
 
                .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
                .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+               .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+               .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02),         // 1 bits
 
                .r_ucsra = UCSR0A,
                .r_ucsrb = UCSR0B,
@@ -136,6 +138,8 @@ struct mcu_t {
 
                .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
                .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
+               .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
+               .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12),         // 1 bits
 
                .r_ucsra = UCSR1A,
                .r_ucsrb = UCSR1B,

diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index b2a892d7fa192aeb90657af46121d92a2a7b7bbd..72599e31bd6dfb8c4fc407b17261071565d5e138 100644 (file)
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -121,6 +121,8 @@ struct mcu_t SIM_CORENAME = {
 
                .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
                .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+               .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+               .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02),         // 1 bits
 
                .r_ucsra = UCSR0A,
                .r_ucsrb = UCSR0B,
@@ -150,6 +152,8 @@ struct mcu_t SIM_CORENAME = {
 
                .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
                .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
+               .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
+               .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12),         // 1 bits
 
                .r_ucsra = UCSR1A,
                .r_ucsrb = UCSR1B,

diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index 280249f1f27adefd5d3c83bb122bbe8352337604..c78874c7191b4314b46011098887edd807b99402 100644 (file)
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -114,6 +114,9 @@ struct mcu_t SIM_CORENAME = {
 
                .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
                .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+               .usbs = AVR_IO_REGBIT(UCSR0C, USBS0),
+               .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+               .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02),         // 1 bits
 
                .r_ucsra = UCSR0A,
                .r_ucsrb = UCSR0B,

diff --git a/simavr/cores/sim_tiny2313.c b/simavr/cores/sim_tiny2313.c
index d9136f3e93dff3ebc9712f9d74d21629cde4533d..faeffd1e2ab55c62e5b5b149d022bf9daf6dc2e2 100644 (file)
--- a/simavr/cores/sim_tiny2313.c
+++ b/simavr/cores/sim_tiny2313.c
@@ -83,6 +83,8 @@ static struct mcu_t {
 
                .txen = AVR_IO_REGBIT(UCSRB, TXEN),
                .rxen = AVR_IO_REGBIT(UCSRB, RXEN),
+               .ucsz = AVR_IO_REGBITS(UCSRC, UCSZ0, 0x3), // 2 bits
+               .ucsz2 = AVR_IO_REGBIT(UCSRB, UCSZ2),   // 1 bits
 
                .r_ucsra = UCSRA,
                .r_ucsrb = UCSRB,