a384d39e32edfa5a7df6356d3421d8cd8663f299

Polled interrupts as for the UART were borken. Now fixed.

Signed-off-by: Michel Pollet <buserror@gmail.com>

diff --git a/simavr/sim/sim_interrupts.c b/simavr/sim/sim_interrupts.c
index 3e094e51f14f466a55b24d0071aebe7b06105b48..9334b038ed1264bfa4b5570041a5541603ff21fe 100644 (file)
--- a/simavr/sim/sim_interrupts.c
+++ b/simavr/sim/sim_interrupts.c
@@ -103,18 +103,18 @@ avr_raise_interrupt(
        if (vector->raised.reg)
                avr_regbit_set(avr, vector->raised);
 
-       // Mark the interrupt as pending
-       vector->pending = 1;
-
-       avr_int_table_p table = &avr->interrupts;
-
-       table->pending[table->pending_w++] = vector;
-       table->pending_w = INT_FIFO_MOD(table->pending_w);
-
        avr_raise_irq(&vector->irq, 1);
 
        // If the interrupt is enabled, attempt to wake the core
        if (avr_regbit_get(avr, vector->enable)) {
+               // Mark the interrupt as pending
+               vector->pending = 1;
+
+               avr_int_table_p table = &avr->interrupts;
+
+               table->pending[table->pending_w++] = vector;
+               table->pending_w = INT_FIFO_MOD(table->pending_w);
+
                if (!table->pending_wait)
                        table->pending_wait = 1;                // latency on interrupts ??
                if (avr->state != cpu_Running) {