bffb2e8ccbd919d058ed408ba67fbe441c17a70e

PCINT8 was previously not setup. Per the spec sheet it is on Port E pin
0.

diff --git a/simavr/cores/sim_mega128rfa1.c b/simavr/cores/sim_mega128rfa1.c
index 69046892ff4ea5545e15568705fc01b13383b8b4..3a14079f5c071fd1155463312afef3e58f0b9039 100644 (file)
--- a/simavr/cores/sim_mega128rfa1.c
+++ b/simavr/cores/sim_mega128rfa1.c
@@ -93,6 +93,12 @@ const struct mcu_t {
        },
        .porte = {
                .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
+               .pcint = {
+                       .enable = AVR_IO_REGBIT(PCICR, PCIE1),
+                       .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
+                       .vector = PCINT1_vect,
+               },
+               .r_pcint = PCMSK1,
        },
        .portf = {
                .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,

diff --git a/simavr/cores/sim_mega128rfr2.c b/simavr/cores/sim_mega128rfr2.c
index 63d5832cfa4b915fbee89d260fdaa744d2f09d7d..d4c8183b09f033487fb4db9c7cb65486abac071b 100644 (file)
--- a/simavr/cores/sim_mega128rfr2.c
+++ b/simavr/cores/sim_mega128rfr2.c
@@ -93,6 +93,12 @@ const struct mcu_t {
        },
        .porte = {
                .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
+               .pcint = {
+                       .enable = AVR_IO_REGBIT(PCICR, PCIE1),
+                       .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
+                       .vector = PCINT1_vect,
+               },
+               .r_pcint = PCMSK1,
        },
        .portf = {
                .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,