},\
}
+/*
+ * no EEPM registers in atmega128
+ */
+#define AVR_EEPROM_DECLARE_NOEEPM(_vector) \
+ .eeprom = {\
+ .size = E2END+1,\
+ .r_eearh = EEARH,\
+ .r_eearl = EEARL,\
+ .r_eedr = EEDR,\
+ .r_eecr = EECR,\
+ .eepm = { }, \
+ .eempe = AVR_IO_REGBIT(EECR, EEMWE),\
+ .eepe = AVR_IO_REGBIT(EECR, EEWE),\
+ .eere = AVR_IO_REGBIT(EECR, EERE),\
+ .ready = {\
+ .enable = AVR_IO_REGBIT(EECR, EERIE),\
+ .vector = _vector,\
+ },\
+ }
+
+
/*
* macro definition without a high address bit register,
* which is not implemented in some tiny AVRs.
},\
}
+/* no WDP3, WDIE, WDIF in atmega128 */
+#define AVR_WATCHDOG_DECLARE_128(_WDSR, _vec) \
+ .watchdog = {\
+ .wdrf = AVR_IO_REGBIT(MCUSR, WDRF),\
+ .wdce = AVR_IO_REGBIT(_WDSR, WDCE),\
+ .wde = AVR_IO_REGBIT(_WDSR, WDE),\
+ .wdp = { AVR_IO_REGBIT(_WDSR, WDP0),AVR_IO_REGBIT(_WDSR, WDP1),\
+ AVR_IO_REGBIT(_WDSR, WDP2) },\
+ .watchdog = {\
+ .enable = AVR_IO_REGBIT(_WDSR, 6),\
+ .raised = AVR_IO_REGBIT(_WDSR, 7),\
+ .vector = _vec,\
+ },\
+ }
+
#endif /* __AVR_WATCHDOG_H___ */