d9d02b63eb3223c1d10cffa068f2da6b8ee5a576

New sreg is local based, should speed up things even more.

Signed-off-by: Michel Pollet <buserror@gmail.com>

diff --git a/simavr/jit_wrapper.c b/simavr/jit_wrapper.c
index a22614711500784b027a85be3e73b1c821e6c5ec..5a1c23c462c3eedc05c8a3545d84777d1c28a4d9 100644 (file)
--- a/simavr/jit_wrapper.c
+++ b/simavr/jit_wrapper.c
@@ -31,8 +31,14 @@ enum {
 };
 
 
-#define SREG_BIT(_b)           (avr_data[R_SREG] & (1 << (_b)))
-#define SREG_SETBIT(_b, _v)    avr_data[R_SREG] = (avr_data[R_SREG] & ~(1 << (_b))) | (!!(_v) << (_b));
+#define SREG_BIT(_b)           (_sreg & (1 << (_b)))
+#define SREG_SETBIT(_b, _v)    _sreg = (_sreg & ~(1 << (_b))) | (!!(_v) << (_b))
+
+#define READ_SREG_INTO(_avr, _dst) \
+       (_dst) = (avr_data)[R_SREG]
+
+#define SREG_START(_avr)       uint8_t _sreg; READ_SREG_INTO(_avr, _sreg)
+#define SREG_END(_avr)         (avr_data)[R_SREG] = _sreg
 
 /*
  * Core states.
@@ -60,8 +66,9 @@ typedef char int8_t;
 typedef unsigned long avr_flashaddr_t;
 
 const char * avr_regname(uint8_t reg);
-void _avr_set_r(
+uint8_t _avr_set_r(
        void * avr,
+       uint8_t _sreg,
        uint16_t r,
        uint8_t v);
 void
@@ -100,27 +107,20 @@ _avr_flash_read16le(
 {
        return (avr_flash[addr] | (avr_flash[addr + 1] << 8));
 }
-static inline void
-_avr_set_r16le(
-       void * ignore,
-       uint16_t r,
-       uint16_t v)
-{
-       _avr_set_r(avr, r, v);
-       _avr_set_r(avr, r + 1, v >> 8);
-}
+#define _avr_set_r16le(_r, _v) \
+       { uint16_t __r = (_r), __v = (_v); \
+       _sreg = _avr_set_r(avr, _sreg, __r, __v); \
+       _sreg = _avr_set_r(avr, _sreg, __r + 1, __v >> 8); }
 
-static inline void
-_avr_set_r16le_hl(
-       void * ignore,
-       uint16_t r,
-       uint16_t v)
-{
-       _avr_set_r(avr, r + 1, v >> 8);
-       _avr_set_r(avr, r , v);
-}
+#define _avr_set_r16le_hl(_r, _v) \
+       { uint16_t __r = (_r), __v = (_v); \
+       _sreg = _avr_set_r(avr, _sreg, __r + 1, __v >> 8); \
+       _sreg = _avr_set_r(avr, _sreg, __r , __v); }
 
 
+/*
+ * Stack pointer access
+ */
 inline uint16_t _avr_sp_get(void * ignore)
 {
        return avr_data[R_SPL] | (avr_data[R_SPH] << 8);
@@ -128,18 +128,21 @@ inline uint16_t _avr_sp_get(void * ignore)
 
 inline void _avr_sp_set(void * ignore, uint16_t sp)
 {
-       _avr_set_r16le(avr, R_SPL, sp);
+       SREG_START(avr);
+       _avr_set_r16le(R_SPL, sp);
+       SREG_END(avr);
 }
 
 /*
  * Set any address to a value; split between registers and SRAM
  */
-static inline void _avr_set_ram(void * ignore, uint16_t addr, uint8_t v)
+static inline uint8_t _avr_set_ram(void * ignore, uint8_t _sreg, uint16_t addr, uint8_t v)
 {
        if (addr < MAX_IOs + 31)
-               _avr_set_r(avr, addr, v);
+               _sreg = _avr_set_r(avr, _sreg, addr, v);
        else
                avr_core_watch_write(avr, addr, v);
+       return _sreg;
 }
 
 #define avr_sreg_set(_ignore, flag, ival) \
@@ -161,7 +164,7 @@ _avr_push8(
        uint16_t v)
 {
        uint16_t sp = _avr_sp_get(avr);
-       _avr_set_ram(avr, sp, v);
+       _avr_set_ram(avr, 0, sp, v);
        _avr_sp_set(avr, sp-1);
 }
 
@@ -197,7 +200,7 @@ _avr_push_addr(
        uint16_t sp = _avr_sp_get(avr);
        addr >>= 1;
        for (int i = 0; i < avr_address_size; i++, addr >>= 8, sp--) {
-               _avr_set_ram(avr, sp, addr);
+               _avr_set_ram(avr, 0, sp, addr);
        }
        _avr_sp_set(avr, sp);
        return avr_address_size;
@@ -210,24 +213,29 @@ _avr_push_addr(
  *
 \****************************************************************************/
 
-static  void
-_avr_flags_zns (void * ignore, uint8_t res)
+/* this flushes the caches SREG, call something then reload into the cache */
+#define SREG_FLUSH(__what) { SREG_END(avr); __what ; READ_SREG_INTO(avr, _sreg); }
+
+static  uint8_t
+_avr_flags_zns (uint8_t _sreg, uint8_t res)
 {
        SREG_SETBIT(S_Z, res == 0);
        SREG_SETBIT(S_N, (res >> 7) & 1);
        SREG_SETBIT(S_S, SREG_BIT(S_N) ^ SREG_BIT(S_V));
+       return _sreg;
 }
 
-static  void
-_avr_flags_zns16 (void * ignore, uint16_t res)
+static  uint8_t
+_avr_flags_zns16 (uint8_t _sreg, uint16_t res)
 {
        SREG_SETBIT(S_Z, res == 0);
        SREG_SETBIT(S_N, (res >> 15) & 1);
        SREG_SETBIT(S_S, SREG_BIT(S_N) ^ SREG_BIT(S_V));
+       return _sreg;
 }
 
-static  void
-_avr_flags_add_zns (void * ignore, uint8_t res, uint8_t rd, uint8_t rr)
+static  uint8_t
+_avr_flags_add_zns (uint8_t _sreg, uint8_t res, uint8_t rd, uint8_t rr)
 {
        /* carry & half carry */
        uint8_t add_carry = (rd & rr) | (rr & ~res) | (~res & rd);
@@ -236,14 +244,13 @@ _avr_flags_add_zns (void * ignore, uint8_t res, uint8_t rd, uint8_t rr)
 
        /* overflow */
        SREG_SETBIT(S_V, (((rd & rr & ~res) | (~rd & ~rr & res)) >> 7) & 1);
-
        /* zns */
-       _avr_flags_zns(avr, res);
+       return _avr_flags_zns(_sreg, res);
 }
 
 
-static  void
-_avr_flags_sub_zns (void * ignore, uint8_t res, uint8_t rd, uint8_t rr)
+static  uint8_t
+_avr_flags_sub_zns (uint8_t _sreg, uint8_t res, uint8_t rd, uint8_t rr)
 {
        /* carry & half carry */
        uint8_t sub_carry = (~rd & rr) | (rr & res) | (res & ~rd);
@@ -254,54 +261,58 @@ _avr_flags_sub_zns (void * ignore, uint8_t res, uint8_t rd, uint8_t rr)
        SREG_SETBIT(S_V, (((rd & ~rr & ~res) | (~rd & rr & res)) >> 7) & 1);
 
        /* zns */
-       _avr_flags_zns(avr, res);
+       return _avr_flags_zns(_sreg, res);
 }
 
-static  void
-_avr_flags_Rzns (void * ignore, uint8_t res)
+static  uint8_t
+_avr_flags_Rzns (uint8_t _sreg, uint8_t res)
 {
        if (res)
                SREG_SETBIT(S_Z, 0);
        SREG_SETBIT(S_N, (res >> 7) & 1);
        SREG_SETBIT(S_S, SREG_BIT(S_N) ^ SREG_BIT(S_V));
+       return _sreg;
 }
 
-static  void
-_avr_flags_sub_Rzns (void * ignore, uint8_t res, uint8_t rd, uint8_t rr)
+static  uint8_t
+_avr_flags_sub_Rzns (uint8_t _sreg, uint8_t res, uint8_t rd, uint8_t rr)
 {
        /* carry & half carry */
        uint8_t sub_carry = (~rd & rr) | (rr & res) | (res & ~rd);
        SREG_SETBIT(S_H, (sub_carry >> 3) & 1);
        SREG_SETBIT(S_C, (sub_carry >> 7) & 1);
+
        /* overflow */
        SREG_SETBIT(S_V, (((rd & ~rr & ~res) | (~rd & rr & res)) >> 7) & 1);
-       _avr_flags_Rzns(avr, res);
+       return _avr_flags_Rzns(_sreg, res);
 }
 
-static  void
-_avr_flags_zcvs (void * ignore, uint8_t res, uint8_t vr)
+static  uint8_t
+_avr_flags_zcvs (uint8_t _sreg, uint8_t res, uint8_t vr)
 {
        SREG_SETBIT(S_Z, res == 0);
        SREG_SETBIT(S_C, vr & 1);
        SREG_SETBIT(S_V, SREG_BIT(S_N) ^ SREG_BIT(S_C));
        SREG_SETBIT(S_S, SREG_BIT(S_N) ^ SREG_BIT(S_V));
+       return _sreg;
 }
 
-static  void
-_avr_flags_zcnvs (void * ignore, uint8_t res, uint8_t vr)
+static  uint8_t
+_avr_flags_zcnvs (uint8_t _sreg, uint8_t res, uint8_t vr)
 {
        SREG_SETBIT(S_Z, res == 0);
        SREG_SETBIT(S_C, vr & 1);
        SREG_SETBIT(S_N, res >> 7);
        SREG_SETBIT(S_V, SREG_BIT(S_N) ^ SREG_BIT(S_C));
        SREG_SETBIT(S_S, SREG_BIT(S_N) ^ SREG_BIT(S_V));
+       return _sreg;
 }
 
-static  void
-_avr_flags_znv0s (void * ignore, uint8_t res)
+static  uint8_t
+_avr_flags_znv0s (uint8_t _sreg, uint8_t res)
 {
        SREG_SETBIT(S_V, 0);
-       _avr_flags_zns(avr, res);
+       return _avr_flags_zns(_sreg, res);
 }
 
 
@@ -391,6 +402,7 @@ firmware(
        int cycle = 0;
 
        jit_avr = _jit_avr;
+       SREG_START(_jit_avr);
 
 //     printf("Hi There %p %p\n", avr_flash, avr_data);
 
@@ -398,5 +410,6 @@ firmware(
 
 exit:
        *cycles += cycle;
+       SREG_END(avr);
        return new_pc;
 }

diff --git a/simavr/sim/sim_core.c b/simavr/sim/sim_core.c
index 6dadac0458b03ee7a70b7123bcb165d6c9d71860..281914e84fd338822c07a206a3c5c84f45586a83 100644 (file)
--- a/simavr/sim/sim_core.c
+++ b/simavr/sim/sim_core.c
@@ -193,8 +193,9 @@ uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
  * if it's an IO register (> 31) also (try to) call any callback that was
  * registered to track changes to that register.
  */
-void _avr_set_r(
+uint8_t _avr_set_r(
        avr_t * avr,
+       uint8_t _sreg,
        uint16_t r,
        uint8_t v)
 {
@@ -680,12 +681,12 @@ run_one_again:
        switch (opcode & 0xf000) {
                case 0x0000: {
                        switch (opcode) {
-                               case 0x0000: {  // NOP
+                               case 0x0000: emit {     // NOP
                                        STATE("nop\n");
-                               }       break;
+                               }       end_emit;
                                default: {
                                        switch (opcode & 0xfc00) {
-                                               case 0x0400: {  // CPC -- Compare with carry -- 0000 01rd dddd rrrr
+                                               case 0x0400: emit {     // CPC -- Compare with carry -- 0000 01rd dddd rrrr
                                                        get_vd5_vr5(opcode);
                                                        uint8_t res = vd - vr - SREG_BIT(S_C);
                                                        STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
@@ -719,14 +720,14 @@ run_one_again:
                                                                        uint8_t r = ((opcode) & 0xf) << 1;
                                                                        STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
                                                                        uint16_t vr = avr->data[r] | (avr->data[r + 1] << 8);
-                                                                       _avr_set_r16le(avr, d, vr);
+                                                                       _avr_set_r16le(d, vr);
                                                                }       end_emit;
                                                                case 0x0200: emit {     // MULS -- Multiply Signed -- 0000 0010 dddd rrrr
                                                                        int8_t r = 16 + (opcode & 0xf);
                                                                        int8_t d = 16 + ((opcode >> 4) & 0xf);
                                                                        int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
                                                                        STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
-                                                                       _avr_set_r16le(avr, 0, res);
+                                                                       _avr_set_r16le(0, res);
                                                                        SREG_SETBIT(S_C, (res >> 15) & 1);
                                                                        SREG_SETBIT(S_Z, res == 0);
                                                                        cycle++;
@@ -1036,14 +1037,14 @@ run_one_again:
                                        STATE("lpm %s, (Z[%04x]) = %02x\n", avr_regname(0), z, avr->flash[z]);
                                        cycle += 2; // 3 cycles
                                        _sreg = _avr_set_r(avr, _sreg, 0, avr->flash[z]);
-                               }       break;
+                               }       end_emit;
                                case 0x95d8: {  // ELPM -- Load Program Memory R0 <- (Z) -- 1001 0101 1101 1000
                                        if (!avr->rampz)
                                                _avr_invalid_opcode(avr);
                                        emit {
                                                uint32_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr_rampz] << 16);
                                                STATE("elpm %s, (Z[%02x:%04x])\n", avr_regname(0), z >> 16, z & 0xffff);
-                                               _sreg = _avr_set_r(avr, sreg, 0, avr->flash[z]);
+                                               _sreg = _avr_set_r(avr, _sreg, 0, avr->flash[z]);
                                                cycle += 2; // 3 cycles
                                        }       end_emit;
                                }       break;
@@ -1105,8 +1106,8 @@ run_one_again:
                                                        if (op == 2) x--;
                                                        uint8_t vd = _avr_get_ram(avr, x);
                                                        if (op == 1) x++;
-                                                       _avr_set_r16le_hl(avr, R_XL, x);
-                                                       _avr_set_r(avr, d, vd);
+                                                       _avr_set_r16le_hl(R_XL, x);
+                                                       _sreg = _avr_set_r(avr, _sreg, d, vd);
                                                }       end_emit;
                                                case 0x920c:
                                                case 0x920d:
@@ -1120,7 +1121,7 @@ run_one_again:
                                                        _sreg = _avr_set_ram(avr, _sreg, x, vd);
                                                        if (op == 1) x++;
                                                        _avr_set_r16le_hl( R_XL, x);
-                                               }       break;
+                                               }       end_emit;
                                                case 0x9009:
                                                case 0x900a: emit {     // LD -- Load Indirect from Data using Y -- 1001 000d dddd 10oo
                                                        int op = opcode & 3;
@@ -1133,7 +1134,7 @@ run_one_again:
                                                        if (op == 1) y++;
                                                        _avr_set_r16le_hl( R_YL, y);
                                                        _sreg = _avr_set_r(avr, _sreg, d, vd);
-                                               }       break;
+                                               }       end_emit;
                                                case 0x9209:
                                                case 0x920a: emit {     // ST -- Store Indirect Data Space Y -- 1001 001d dddd 10oo
                                                        int op = opcode & 3;
@@ -1153,7 +1154,7 @@ run_one_again:
                                                        STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(d), vd);
                                                        cycle++;
                                                        _sreg = _avr_set_ram(avr, _sreg, x, vd);
-                                               }       break;
+                                               }       end_emit;
                                                case 0x9001:
                                                case 0x9002: emit {     // LD -- Load Indirect from Data using Z -- 1001 000d dddd 00oo
                                                        int op = opcode & 3;
@@ -1249,8 +1250,8 @@ run_one_again:
                                                        get_vd5(opcode);
                                                        uint8_t res = (SREG_BIT(S_C) ? 0x80 : 0) | vd >> 1;
                                                        STATE("ror %s[%02x]\n", avr_regname(d), vd);
-                                                       _avr_set_r(avr, d, res);
-                                                       _avr_flags_zcnvs(avr, res, vd);
+                                                       _sreg = _avr_set_r(avr, _sreg, d, res);
+                                                       _sreg = _avr_flags_zcnvs(_sreg, res, vd);
                                                        SREG();
                                                }       end_emit;
                                                case 0x940a: emit {     // DEC -- Decrement -- 1001 010d dddd 1010

diff --git a/simavr/sim/sim_core_jit.c b/simavr/sim/sim_core_jit.c
index de60c8634856f2153636d9d3bfd2e54edd265c3e..dcf2ef49446d65651301b5491f32ed4ceeec89a2 100644 (file)
--- a/simavr/sim/sim_core_jit.c
+++ b/simavr/sim/sim_core_jit.c
@@ -163,6 +163,7 @@ avr_callback_run_jit(
        avr_t * avr)
 {
        avr_flashaddr_t new_pc = avr->pc;
+       SREG_START(avr);
 
        if (avr->state == cpu_Running) {
                int cycle = 0;

diff --git a/simavr/sim/sim_core_jit.h b/simavr/sim/sim_core_jit.h
index 15bf1b1489ef8762f0b961061733779b83c8ac9a..45f7ea242ae9331435934942295ffbf147b649f8 100644 (file)
--- a/simavr/sim/sim_core_jit.h
+++ b/simavr/sim/sim_core_jit.h
@@ -18,7 +18,7 @@ jit_generate(opcode, "STATE(\"nop\\n\");\n"
 jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "uint8_t res = vd - vr - SREG_BIT(S_C);\n"
 "STATE(\"cpc %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), vd, avr_regname(r), vr, res);\n"
-"_avr_flags_sub_Rzns(avr, res, vd, vr);\n"
+"_sreg = _avr_flags_sub_Rzns(_sreg, res, vd, vr);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -30,8 +30,8 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "} else {\n"
 "STATE(\"add %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), vd, avr_regname(r), vr, res);\n"
 "}\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_add_zns(avr, res, vd, vr);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_add_zns(_sreg, res, vd, vr);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -39,8 +39,8 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "uint8_t res = vd - vr - SREG_BIT(S_C);\n"
 "STATE(\"sbc %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), avr_data[d], avr_regname(r), avr_data[r], res);\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_sub_Rzns(avr, res, vd, vr);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_sub_Rzns(_sreg, res, vd, vr);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -51,7 +51,7 @@ jit_generate(opcode, "uint8_t d = ((opcode >> 4) & 0xf) << 1;\n"
 "uint8_t r = ((opcode) & 0xf) << 1;\n"
 "STATE(\"movw %s:%s, %s:%s[%02x%02x]\\n\", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr_data[r+1], avr_data[r]);\n"
 "uint16_t vr = avr_data[r] | (avr_data[r + 1] << 8);\n"
-"_avr_set_r16le(avr, d, vr);\n"
+"_avr_set_r16le(d, vr);\n"
 );
                                                                }       break;
                                                                case 0x0200:  { // MULS -- Multiply Signed -- 0000 0010 dddd rrrr
@@ -59,7 +59,7 @@ jit_generate(opcode, "int8_t r = 16 + (opcode & 0xf);\n"
 "int8_t d = 16 + ((opcode >> 4) & 0xf);\n"
 "int16_t res = ((int8_t)avr_data[r]) * ((int8_t)avr_data[d]);\n"
 "STATE(\"muls %s[%d], %s[%02x] = %d\\n\", avr_regname(d), ((int8_t)avr_data[d]), avr_regname(r), ((int8_t)avr_data[r]), res);\n"
-"_avr_set_r16le(avr, 0, res);\n"
+"_avr_set_r16le(0, res);\n"
 "SREG_SETBIT(S_C, (res >> 15) & 1);\n"
 "SREG_SETBIT(S_Z, res == 0);\n"
 "cycle++;\n"
@@ -99,7 +99,7 @@ jit_generate(opcode, "int8_t r = 16 + (opcode & 0x7);\n"
 "}\n"
 "cycle++;\n"
 "STATE(\"%s %s[%d], %s[%02x] = %d\\n\", name, avr_regname(d), ((int8_t)avr_data[d]), avr_regname(r), ((int8_t)avr_data[r]), res);\n"
-"_avr_set_r16le(avr, 0, res);\n"
+"_avr_set_r16le(0, res);\n"
 "SREG_SETBIT(S_C, c);\n"
 "SREG_SETBIT(S_Z, res == 0);\n"
 "SREG();\n"
@@ -118,8 +118,8 @@ jit_generate(opcode, "int8_t r = 16 + (opcode & 0x7);\n"
 jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "uint8_t res = vd - vr;\n"
 "STATE(\"sub %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), vd, avr_regname(r), vr, res);\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_sub_zns(avr, res, vd, vr);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_sub_zns(_sreg, res, vd, vr);\n"
 "SREG();\n"
 );
                                }       break;
@@ -145,7 +145,7 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "uint8_t res = vd - vr;\n"
 "STATE(\"cp %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), vd, avr_regname(r), vr, res);\n"
-"_avr_flags_sub_zns(avr, res, vd, vr);\n"
+"_sreg = _avr_flags_sub_zns(_sreg, res, vd, vr);\n"
 "SREG();\n"
 );
                                }       break;
@@ -157,8 +157,8 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "} else {\n"
 "STATE(\"addc %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), avr_data[d], avr_regname(r), avr_data[r], res);\n"
 "}\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_add_zns(avr, res, vd, vr);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_add_zns(_sreg, res, vd, vr);\n"
 "SREG();\n"
 );
                                }       break;
@@ -176,8 +176,8 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "} else {\n"
 "STATE(\"and %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), vd, avr_regname(r), vr, res);\n"
 "}\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_znv0s(avr, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_znv0s(_sreg, res);\n"
 "SREG();\n"
 );
                                }       break;
@@ -189,8 +189,8 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "} else {\n"
 "STATE(\"eor %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), vd, avr_regname(r), vr, res);\n"
 "}\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_znv0s(avr, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_znv0s(_sreg, res);\n"
 "SREG();\n"
 );
                                }       break;
@@ -198,8 +198,8 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "uint8_t res = vd | vr;\n"
 "STATE(\"or %s[%02x], %s[%02x] = %02x\\n\", avr_regname(d), vd, avr_regname(r), vr, res);\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_znv0s(avr, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_znv0s(_sreg, res);\n"
 "SREG();\n"
 );
                                }       break;
@@ -207,7 +207,7 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 jit_generate(opcode, "get_d5_vr5(opcode);\n"
 "uint8_t res = vr;\n"
 "STATE(\"mov %s, %s[%02x] = %02x\\n\", avr_regname(d), avr_regname(r), vr, res);\n"
-"_avr_set_r(avr, d, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
 );
                                }       break;
                                default: _avr_invalid_opcode(avr);
@@ -218,7 +218,7 @@ jit_generate(opcode, "get_d5_vr5(opcode);\n"
 jit_generate(opcode, "get_vh4_k8(opcode);\n"
 "uint8_t res = vh - k;\n"
 "STATE(\"cpi %s[%02x], 0x%02x\\n\", avr_regname(h), vh, k);\n"
-"_avr_flags_sub_zns(avr, res, vh, k);\n"
+"_sreg = _avr_flags_sub_zns(_sreg, res, vh, k);\n"
 "SREG();\n"
 );
                }       break;
@@ -227,8 +227,8 @@ jit_generate(opcode, "get_vh4_k8(opcode);\n"
 jit_generate(opcode, "get_vh4_k8(opcode);\n"
 "uint8_t res = vh - k - SREG_BIT(S_C);\n"
 "STATE(\"sbci %s[%02x], 0x%02x = %02x\\n\", avr_regname(h), vh, k, res);\n"
-"_avr_set_r(avr, h, res);\n"
-"_avr_flags_sub_Rzns(avr, res, vh, k);\n"
+"_sreg = _avr_set_r(avr, _sreg, h, res);\n"
+"_sreg = _avr_flags_sub_Rzns(_sreg, res, vh, k);\n"
 "SREG();\n"
 );
                }       break;
@@ -237,8 +237,8 @@ jit_generate(opcode, "get_vh4_k8(opcode);\n"
 jit_generate(opcode, "get_vh4_k8(opcode);\n"
 "uint8_t res = vh - k;\n"
 "STATE(\"subi %s[%02x], 0x%02x = %02x\\n\", avr_regname(h), vh, k, res);\n"
-"_avr_set_r(avr, h, res);\n"
-"_avr_flags_sub_zns(avr, res, vh, k);\n"
+"_sreg = _avr_set_r(avr, _sreg, h, res);\n"
+"_sreg = _avr_flags_sub_zns(_sreg, res, vh, k);\n"
 "SREG();\n"
 );
                }       break;
@@ -247,8 +247,8 @@ jit_generate(opcode, "get_vh4_k8(opcode);\n"
 jit_generate(opcode, "get_vh4_k8(opcode);\n"
 "uint8_t res = vh | k;\n"
 "STATE(\"ori %s[%02x], 0x%02x\\n\", avr_regname(h), vh, k);\n"
-"_avr_set_r(avr, h, res);\n"
-"_avr_flags_znv0s(avr, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, h, res);\n"
+"_sreg = _avr_flags_znv0s(_sreg, res);\n"
 "SREG();\n"
 );
                }       break;
@@ -257,8 +257,8 @@ jit_generate(opcode, "get_vh4_k8(opcode);\n"
 jit_generate(opcode, "get_vh4_k8(opcode);\n"
 "uint8_t res = vh & k;\n"
 "STATE(\"andi %s[%02x], 0x%02x\\n\", avr_regname(h), vh, k);\n"
-"_avr_set_r(avr, h, res);\n"
-"_avr_flags_znv0s(avr, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, h, res);\n"
+"_sreg = _avr_flags_znv0s(_sreg, res);\n"
 "SREG();\n"
 );
                }       break;
@@ -280,10 +280,10 @@ jit_generate(opcode, "uint16_t v = avr_data[R_ZL] | (avr_data[R_ZH] << 8);\n"
 "get_d5_q6(opcode);\n"
 "if (opcode & 0x0200) {\n"
 "STATE(\"st (Z+%d[%04x]), %s[%02x]\\n\", q, v+q, avr_regname(d), avr_data[d]);\n"
-"_avr_set_ram(avr, v+q, avr_data[d]);\n"
+"_sreg = _avr_set_ram(avr, _sreg, v+q, avr_data[d]);\n"
 "} else {\n"
 "STATE(\"ld %s, (Z+%d[%04x])=[%02x]\\n\", avr_regname(d), q, v+q, avr_data[v+q]);\n"
-"_avr_set_r(avr, d, _avr_get_ram(avr, v+q));\n"
+"_sreg = _avr_set_r(avr, _sreg, d, _avr_get_ram(avr, v+q));\n"
 "}\n"
 "cycle += 1; // 2 cycles, 3 for tinyavr\n"
 );
@@ -294,10 +294,10 @@ jit_generate(opcode, "uint16_t v = avr_data[R_YL] | (avr_data[R_YH] << 8);\n"
 "get_d5_q6(opcode);\n"
 "if (opcode & 0x0200) {\n"
 "STATE(\"st (Y+%d[%04x]), %s[%02x]\\n\", q, v+q, avr_regname(d), avr_data[d]);\n"
-"_avr_set_ram(avr, v+q, avr_data[d]);\n"
+"_sreg = _avr_set_ram(avr, _sreg, v+q, avr_data[d]);\n"
 "} else {\n"
 "STATE(\"ld %s, (Y+%d[%04x])=[%02x]\\n\", avr_regname(d), q, v+q, avr_data[d+q]);\n"
-"_avr_set_r(avr, d, _avr_get_ram(avr, v+q));\n"
+"_sreg = _avr_set_r(avr, _sreg, d, _avr_get_ram(avr, v+q));\n"
 "}\n"
 "cycle += 1; // 2 cycles, 3 for tinyavr\n"
 );
@@ -325,7 +325,7 @@ jit_generate(opcode, "STATE(\"sleep\\n\");\n"
 "* details, see the commit message. */\n"
 "if (!avr_has_pending_interrupts(avr) || !SREG_BIT(S_I)) {\n"
 "avr_state = cpu_Sleeping;\n"
-"CORE_SLEEP();\n"
+"SREG_FLUSH(CORE_SLEEP(););\n"
 "}\n"
 );
                                }       break;
@@ -343,12 +343,12 @@ jit_generate(opcode, "STATE(\"break\\n\");\n"
                                }       break;
                                case 0x95a8:  { // WDR -- Watchdog Reset -- 1001 0101 1010 1000
 jit_generate(opcode, "STATE(\"wdr\\n\");\n"
-"avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0);\n"
+"SREG_FLUSH(avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0));\n"
 );
                                }       break;
                                case 0x95e8:  { // SPM -- Store Program Memory -- 1001 0101 1110 1000
 jit_generate(opcode, "STATE(\"spm\\n\");\n"
-"avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);\n"
+"SREG_FLUSH(avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0));\n"
 );
                                }       break;
                                case 0x9409:   // IJMP -- Indirect jump -- 1001 0100 0000 1001
@@ -377,8 +377,9 @@ jit_generate(opcode, "uint32_t z = avr_data[R_ZL] | (avr_data[R_ZH] << 8);\n"
                                case 0x9508:            // RET -- Return -- 1001 0101 0000 1000
                                case 0x9518:  { // RETI -- Return from Interrupt -- 1001 0101 0001 1000
 jit_generate(opcode, "if (opcode == 0x9518) {\n"
+"SREG_FLUSH(\n"
 "avr_sreg_set(avr, S_I, 1);\n"
-"avr_interrupt_reti(avr);\n"
+"avr_interrupt_reti(avr) );\n"
 "}\n"
 "new_pc = _avr_pop_addr(avr);\n"
 "cycle += 1 + avr_address_size;\n"
@@ -391,16 +392,16 @@ jit_generate(opcode, "if (opcode == 0x9518) {\n"
 jit_generate(opcode, "uint16_t z = avr_data[R_ZL] | (avr_data[R_ZH] << 8);\n"
 "STATE(\"lpm %s, (Z[%04x]) = %02x\\n\", avr_regname(0), z, avr_flash[z]);\n"
 "cycle += 2; // 3 cycles\n"
-"_avr_set_r(avr, 0, avr_flash[z]);\n"
+"_sreg = _avr_set_r(avr, _sreg, 0, avr_flash[z]);\n"
 );
                                }       break;
                                case 0x95d8: {  // ELPM -- Load Program Memory R0 <- (Z) -- 1001 0101 1101 1000
-                                       if (!avr_rampz)
+                                       if (!avr->rampz)
                                                _avr_invalid_opcode(avr);
                                         {
 jit_generate(opcode, "uint32_t z = avr_data[R_ZL] | (avr_data[R_ZH] << 8) | (avr_data[avr_rampz] << 16);\n"
 "STATE(\"elpm %s, (Z[%02x:%04x])\\n\", avr_regname(0), z >> 16, z & 0xffff);\n"
-"_avr_set_r(avr, 0, avr_flash[z]);\n"
+"_sreg = _avr_set_r(avr, _sreg, 0, avr_flash[z]);\n"
 "cycle += 2; // 3 cycles\n"
 );
                                        }       break;
@@ -412,7 +413,7 @@ jit_generate(opcode, "get_d5(opcode);\n"
 "uint16_t x = _avr_flash_read16le(avr, new_pc);\n"
 "new_pc += 2;\n"
 "STATE(\"lds %s[%02x], 0x%04x\\n\", avr_regname(d), avr_data[d], x);\n"
-"_avr_set_r(avr, d, _avr_get_ram(avr, x));\n"
+"_sreg = _avr_set_r(avr, _sreg, d, _avr_get_ram(avr, x));\n"
 "cycle++; // 2 cycles\n"
 );
                                                }       break;
@@ -421,10 +422,10 @@ jit_generate(opcode, "get_d5(opcode);\n"
 jit_generate(opcode, "get_d5(opcode);\n"
 "uint16_t z = avr_data[R_ZL] | (avr_data[R_ZH] << 8);\n"
 "int op = opcode & 1;\n"
-"STATE(\"lpm %s, (Z[%04x]%s) = %02x\\n\", avr_regname(d), z, op ? \"+\" : \"\", avr_flash[z]);\n"
-"_avr_set_r(avr, d, avr_flash[z]);\n"
+"STATE(\"lpm %s, (Z[%04x]%s)\\n\", avr_regname(d), z, op ? \"+\" : \"\");\n"
+"_sreg = _avr_set_r(avr, _sreg, d, avr_flash[z]);\n"
 "if (op)\n"
-"_avr_set_r16le_hl(avr, R_ZL, z + 1);\n"
+"_avr_set_r16le_hl( R_ZL, z + 1);\n"
 "cycle += 2; // 3 cycles\n"
 );
                                                }       break;
@@ -437,11 +438,11 @@ jit_generate(opcode, "uint32_t z = avr_data[R_ZL] | (avr_data[R_ZH] << 8) | (avr
 "get_d5(opcode);\n"
 "int op = opcode & 1;\n"
 "STATE(\"elpm %s, (Z[%02x:%04x]%s)\\n\", avr_regname(d), z >> 16, z & 0xffff, op ? \"+\" : \"\");\n"
-"_avr_set_r(avr, d, avr_flash[z]);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, avr_flash[z]);\n"
 "if (op) {\n"
 "z++;\n"
-"_avr_set_r(avr, avr_rampz, z >> 16);\n"
-"_avr_set_r16le_hl(avr, R_ZL, z);\n"
+"_sreg = _avr_set_r(avr, _sreg, avr->rampz, z >> 16);\n"
+"_avr_set_r16le_hl( R_ZL, z);\n"
 "}\n"
 "cycle += 2; // 3 cycles\n"
 );
@@ -466,8 +467,8 @@ jit_generate(opcode, "int op = opcode & 3;\n"
 "if (op == 2) x--;\n"
 "uint8_t vd = _avr_get_ram(avr, x);\n"
 "if (op == 1) x++;\n"
-"_avr_set_r16le_hl(avr, R_XL, x);\n"
-"_avr_set_r(avr, d, vd);\n"
+"_avr_set_r16le_hl(R_XL, x);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, vd);\n"
 );
                                                }       break;
                                                case 0x920c:
@@ -479,9 +480,9 @@ jit_generate(opcode, "int op = opcode & 3;\n"
 "STATE(\"st %sX[%04x]%s, %s[%02x] \\n\", op == 2 ? \"--\" : \"\", x, op == 1 ? \"++\" : \"\", avr_regname(d), vd);\n"
 "cycle++; // 2 cycles, except tinyavr\n"
 "if (op == 2) x--;\n"
-"_avr_set_ram(avr, x, vd);\n"
+"_sreg = _avr_set_ram(avr, _sreg, x, vd);\n"
 "if (op == 1) x++;\n"
-"_avr_set_r16le_hl(avr, R_XL, x);\n"
+"_avr_set_r16le_hl( R_XL, x);\n"
 );
                                                }       break;
                                                case 0x9009:
@@ -494,8 +495,8 @@ jit_generate(opcode, "int op = opcode & 3;\n"
 "if (op == 2) y--;\n"
 "uint8_t vd = _avr_get_ram(avr, y);\n"
 "if (op == 1) y++;\n"
-"_avr_set_r16le_hl(avr, R_YL, y);\n"
-"_avr_set_r(avr, d, vd);\n"
+"_avr_set_r16le_hl( R_YL, y);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, vd);\n"
 );
                                                }       break;
                                                case 0x9209:
@@ -506,9 +507,9 @@ jit_generate(opcode, "int op = opcode & 3;\n"
 "STATE(\"st %sY[%04x]%s, %s[%02x]\\n\", op == 2 ? \"--\" : \"\", y, op == 1 ? \"++\" : \"\", avr_regname(d), vd);\n"
 "cycle++;\n"
 "if (op == 2) y--;\n"
-"_avr_set_ram(avr, y, vd);\n"
+"_sreg = _avr_set_ram(avr, _sreg, y, vd);\n"
 "if (op == 1) y++;\n"
-"_avr_set_r16le_hl(avr, R_YL, y);\n"
+"_avr_set_r16le_hl( R_YL, y);\n"
 );
                                                }       break;
                                                case 0x9200:  { // STS -- Store Direct to Data Space, 32 bits -- 1001 0010 0000 0000
@@ -517,7 +518,7 @@ jit_generate(opcode, "get_vd5(opcode);\n"
 "new_pc += 2;\n"
 "STATE(\"sts 0x%04x, %s[%02x]\\n\", x, avr_regname(d), vd);\n"
 "cycle++;\n"
-"_avr_set_ram(avr, x, vd);\n"
+"_sreg = _avr_set_ram(avr, _sreg, x, vd);\n"
 );
                                                }       break;
                                                case 0x9001:
@@ -530,8 +531,8 @@ jit_generate(opcode, "int op = opcode & 3;\n"
 "if (op == 2) z--;\n"
 "uint8_t vd = _avr_get_ram(avr, z);\n"
 "if (op == 1) z++;\n"
-"_avr_set_r16le_hl(avr, R_ZL, z);\n"
-"_avr_set_r(avr, d, vd);\n"
+"_avr_set_r16le_hl( R_ZL, z);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, vd);\n"
 );
                                                }       break;
                                                case 0x9201:
@@ -542,14 +543,14 @@ jit_generate(opcode, "int op = opcode & 3;\n"
 "STATE(\"st %sZ[%04x]%s, %s[%02x] \\n\", op == 2 ? \"--\" : \"\", z, op == 1 ? \"++\" : \"\", avr_regname(d), vd);\n"
 "cycle++; // 2 cycles, except tinyavr\n"
 "if (op == 2) z--;\n"
-"_avr_set_ram(avr, z, vd);\n"
+"_sreg = _avr_set_ram(avr, _sreg, z, vd);\n"
 "if (op == 1) z++;\n"
-"_avr_set_r16le_hl(avr, R_ZL, z);\n"
+"_avr_set_r16le_hl( R_ZL, z);\n"
 );
                                                }       break;
                                                case 0x900f:  { // POP -- 1001 000d dddd 1111
 jit_generate(opcode, "get_d5(opcode);\n"
-"_avr_set_r(avr, d, _avr_pop8(avr));\n"
+"_sreg = _avr_set_r(avr, _sreg, d, _avr_pop8(avr));\n"
 "T(uint16_t sp = _avr_sp_get(avr);)\n"
 "STATE(\"pop %s (@%04x)[%02x]\\n\", avr_regname(d), sp, avr_data[sp]);\n"
 "cycle++;\n"
@@ -567,8 +568,8 @@ jit_generate(opcode, "get_vd5(opcode);\n"
 jit_generate(opcode, "get_vd5(opcode);\n"
 "uint8_t res = 0xff - vd;\n"
 "STATE(\"com %s[%02x] = %02x\\n\", avr_regname(d), vd, res);\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_znv0s(avr, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_znv0s(_sreg, res);\n"
 "SREG_SETBIT(S_C, 1);\n"
 "SREG();\n"
 );
@@ -577,11 +578,11 @@ jit_generate(opcode, "get_vd5(opcode);\n"
 jit_generate(opcode, "get_vd5(opcode);\n"
 "uint8_t res = 0x00 - vd;\n"
 "STATE(\"neg %s[%02x] = %02x\\n\", avr_regname(d), vd, res);\n"
-"_avr_set_r(avr, d, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
 "SREG_SETBIT(S_H, ((res >> 3) | (vd >> 3)) & 1);\n"
 "SREG_SETBIT(S_V, res == 0x80);\n"
 "SREG_SETBIT(S_C, res != 0);\n"
-"_avr_flags_zns(avr, res);\n"
+"_sreg = _avr_flags_zns(_sreg, res);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -589,16 +590,16 @@ jit_generate(opcode, "get_vd5(opcode);\n"
 jit_generate(opcode, "get_vd5(opcode);\n"
 "uint8_t res = (vd >> 4) | (vd << 4) ;\n"
 "STATE(\"swap %s[%02x] = %02x\\n\", avr_regname(d), vd, res);\n"
-"_avr_set_r(avr, d, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
 );
                                                }       break;
                                                case 0x9403:  { // INC -- Increment -- 1001 010d dddd 0011
 jit_generate(opcode, "get_vd5(opcode);\n"
 "uint8_t res = vd + 1;\n"
 "STATE(\"inc %s[%02x] = %02x\\n\", avr_regname(d), vd, res);\n"
-"_avr_set_r(avr, d, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
 "SREG_SETBIT(S_V, res == 0x80);\n"
-"_avr_flags_zns(avr, res);\n"
+"_sreg = _avr_flags_zns(_sreg, res);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -606,8 +607,8 @@ jit_generate(opcode, "get_vd5(opcode);\n"
 jit_generate(opcode, "get_vd5(opcode);\n"
 "uint8_t res = (vd >> 1) | (vd & 0x80);\n"
 "STATE(\"asr %s[%02x]\\n\", avr_regname(d), vd);\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_zcnvs(avr, res, vd);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_zcnvs(_sreg, res, vd);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -615,9 +616,9 @@ jit_generate(opcode, "get_vd5(opcode);\n"
 jit_generate(opcode, "get_vd5(opcode);\n"
 "uint8_t res = vd >> 1;\n"
 "STATE(\"lsr %s[%02x]\\n\", avr_regname(d), vd);\n"
-"_avr_set_r(avr, d, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
 "SREG_SETBIT(S_N, 0);\n"
-"_avr_flags_zcvs(avr, res, vd);\n"
+"_sreg = _avr_flags_zcvs(_sreg, res, vd);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -625,8 +626,8 @@ jit_generate(opcode, "get_vd5(opcode);\n"
 jit_generate(opcode, "get_vd5(opcode);\n"
 "uint8_t res = (SREG_BIT(S_C) ? 0x80 : 0) | vd >> 1;\n"
 "STATE(\"ror %s[%02x]\\n\", avr_regname(d), vd);\n"
-"_avr_set_r(avr, d, res);\n"
-"_avr_flags_zcnvs(avr, res, vd);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
+"_sreg = _avr_flags_zcnvs(_sreg, res, vd);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -634,9 +635,9 @@ jit_generate(opcode, "get_vd5(opcode);\n"
 jit_generate(opcode, "get_vd5(opcode);\n"
 "uint8_t res = vd - 1;\n"
 "STATE(\"dec %s[%02x] = %02x\\n\", avr_regname(d), vd, res);\n"
-"_avr_set_r(avr, d, res);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, res);\n"
 "SREG_SETBIT(S_V, res == 0x7f);\n"
-"_avr_flags_zns(avr, res);\n"
+"_sreg = _avr_flags_zns(_sreg, res);\n"
 "SREG();\n"
 );
                                                }       break;
@@ -671,10 +672,10 @@ jit_generate(opcode, "avr_flashaddr_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1
 jit_generate(opcode, "get_vp2_k6(opcode);\n"
 "uint16_t res = vp + k;\n"
 "STATE(\"adiw %s:%s[%04x], 0x%02x\\n\", avr_regname(p), avr_regname(p + 1), vp, k);\n"
-"_avr_set_r16le_hl(avr, p, res);\n"
+"_avr_set_r16le_hl( p, res);\n"
 "SREG_SETBIT(S_V, ((~vp & res) >> 15) & 1);\n"
 "SREG_SETBIT(S_C, ((~res & vp) >> 15) & 1);\n"
-"_avr_flags_zns16(avr, res);\n"
+"_sreg = _avr_flags_zns16(_sreg, res);\n"
 "SREG();\n"
 "cycle++;\n"
 );
@@ -683,10 +684,10 @@ jit_generate(opcode, "get_vp2_k6(opcode);\n"
 jit_generate(opcode, "get_vp2_k6(opcode);\n"
 "uint16_t res = vp - k;\n"
 "STATE(\"sbiw %s:%s[%04x], 0x%02x\\n\", avr_regname(p), avr_regname(p + 1), vp, k);\n"
-"_avr_set_r16le_hl(avr, p, res);\n"
+"_avr_set_r16le_hl( p, res);\n"
 "SREG_SETBIT(S_V, ((vp & ~res) >> 15) & 1);\n"
 "SREG_SETBIT(S_C, ((res & ~vp) >> 15) & 1);\n"
-"_avr_flags_zns16(avr, res);\n"
+"_sreg = _avr_flags_zns16(_sreg, res);\n"
 "SREG();\n"
 "cycle++;\n"
 );
@@ -695,7 +696,7 @@ jit_generate(opcode, "get_vp2_k6(opcode);\n"
 jit_generate(opcode, "get_io5_b3mask(opcode);\n"
 "uint8_t res = _avr_get_ram(avr, io) & ~mask;\n"
 "STATE(\"cbi %s[%04x], 0x%02x = %02x\\n\", avr_regname(io), avr_data[io], mask, res);\n"
-"_avr_set_ram(avr, io, res);\n"
+"_sreg = _avr_set_ram(avr, _sreg, io, res);\n"
 "cycle++;\n"
 );
                                                                }       break;
@@ -717,7 +718,7 @@ jit_generate(opcode, "get_io5_b3mask(opcode);\n"
 jit_generate(opcode, "get_io5_b3mask(opcode);\n"
 "uint8_t res = _avr_get_ram(avr, io) | mask;\n"
 "STATE(\"sbi %s[%04x], 0x%02x = %02x\\n\", avr_regname(io), avr_data[io], mask, res);\n"
-"_avr_set_ram(avr, io, res);\n"
+"_sreg = _avr_set_ram(avr, _sreg, io, res);\n"
 "cycle++;\n"
 );
                                                                }       break;
@@ -742,7 +743,7 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
 "uint16_t res = vd * vr;\n"
 "STATE(\"mul %s[%02x], %s[%02x] = %04x\\n\", avr_regname(d), vd, avr_regname(r), vr, res);\n"
 "cycle++;\n"
-"_avr_set_r16le(avr, 0, res);\n"
+"_avr_set_r16le(0, res);\n"
 "SREG_SETBIT(S_Z, res == 0);\n"
 "SREG_SETBIT(S_C, (res >> 15) & 1);\n"
 "SREG();\n"
@@ -762,13 +763,13 @@ jit_generate(opcode, "get_vd5_vr5(opcode);\n"
                                case 0xb800:  { // OUT A,Rr -- 1011 1AAd dddd AAAA
 jit_generate(opcode, "get_d5_a6(opcode);\n"
 "STATE(\"out %s, %s[%02x]\\n\", avr_regname(A), avr_regname(d), avr_data[d]);\n"
-"_avr_set_ram(avr, A, avr_data[d]);\n"
+"_sreg = _avr_set_ram(avr, _sreg, A, avr_data[d]);\n"
 );
                                }       break;
                                case 0xb000:  { // IN Rd,A -- 1011 0AAd dddd AAAA
 jit_generate(opcode, "get_d5_a6(opcode);\n"
 "STATE(\"in %s, %s[%02x]\\n\", avr_regname(d), avr_regname(A), avr_data[A]);\n"
-"_avr_set_r(avr, d, _avr_get_ram(avr, A));\n"
+"_sreg = _avr_set_r(avr, _sreg, d, _avr_get_ram(avr, A));\n"
 );
                                }       break;
                                default: _avr_invalid_opcode(avr);
@@ -800,7 +801,7 @@ jit_generate(opcode, "get_o12(opcode);\n"
                case 0xe000:  { // LDI Rd, K aka SER (LDI r, 0xff) -- 1110 kkkk dddd kkkk
 jit_generate(opcode, "get_h4_k8(opcode);\n"
 "STATE(\"ldi %s, 0x%02x\\n\", avr_regname(h), k);\n"
-"_avr_set_r(avr, h, k);\n"
+"_sreg = _avr_set_r(avr, _sreg, h, k);\n"
 );
                }       break;
 
@@ -833,7 +834,7 @@ jit_generate(opcode, "int16_t o = ((int16_t)(opcode << 6)) >> 9; // offset\n"
 jit_generate(opcode, "get_vd5_s3_mask(opcode);\n"
 "uint8_t v = (vd & ~mask) | (SREG_BIT(S_T) ? mask : 0);\n"
 "STATE(\"bld %s[%02x], 0x%02x = %02x\\n\", avr_regname(d), vd, mask, v);\n"
-"_avr_set_r(avr, d, v);\n"
+"_sreg = _avr_set_r(avr, _sreg, d, v);\n"
 );
                                }       break;
                                case 0xfa00: