e175b0fd73521fd7acea6267bfe023a407f31da4

convert spi structure definitions to AVR_SPI_DECLARE

	modified:   simavr/cores/sim_90usb162.c
	modified:   simavr/cores/sim_mega128.c
	modified:   simavr/cores/sim_mega1280.c
	modified:   simavr/cores/sim_mega1281.c
	modified:   simavr/cores/sim_mega128rfr2.c
	modified:   simavr/cores/sim_mega169.c
	modified:   simavr/cores/sim_mega2560.c
	modified:   simavr/cores/sim_megax.h
	modified:   simavr/cores/sim_megax4.h
	modified:   simavr/cores/sim_megax8.h
	modified:   simavr/cores/sim_megaxm1.h
	modified:   simavr/sim/avr_spi.h

diff --git a/simavr/cores/sim_90usb162.c b/simavr/cores/sim_90usb162.c
index 3cdc647d36a4c88a61c54fb2a83ab4fd35d65c9b..577a45a8d6852706992a842e11b638b53ae34241 100644 (file)
--- a/simavr/cores/sim_90usb162.c
+++ b/simavr/cores/sim_90usb162.c
@@ -228,22 +228,7 @@ const struct mcu_t {
                        },
                },
        },
-       .spi = {
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
+       AVR_SPI_DECLARE(0, 0),
        .usb = {
                .name='1',
                .disabled=AVR_IO_REGBIT(PRR1, PRUSB),// bit in the PRR

diff --git a/simavr/cores/sim_mega128.c b/simavr/cores/sim_mega128.c
index 355b94101a4c7d5dac8b3a4fc62f113939726ec4..533dfcfd1372cde7ddb261e1a04156d224497eed 100644 (file)
--- a/simavr/cores/sim_mega128.c
+++ b/simavr/cores/sim_mega128.c
@@ -434,23 +434,7 @@ const struct mcu_t {
                        .vector = TIMER3_CAPT_vect,
                },
        },
-       .spi = {
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-       
+       AVR_SPI_DECLARE(0, 0),
        .twi = {
 
                .r_twcr = TWCR,

diff --git a/simavr/cores/sim_mega1280.c b/simavr/cores/sim_mega1280.c
index 9ed040c310608f627dc1055be4da49b628fb0cd5..edbbf396f8c2bbe5797eed5426291695bca3f04e 100644 (file)
--- a/simavr/cores/sim_mega1280.c
+++ b/simavr/cores/sim_mega1280.c
@@ -716,24 +716,7 @@ const struct mcu_t {
                },
 
        },
-       .spi = {
-               .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-
+       AVR_SPI_DECLARE(PRR0, PRSPI),
        .twi = {
 
                .r_twcr = TWCR,

diff --git a/simavr/cores/sim_mega1281.c b/simavr/cores/sim_mega1281.c
index a8a80bb411f4de34c6f301d6ef45b5dde5908d7b..3378865b1f5568397e98a4326fdc000df11d0f9a 100644 (file)
--- a/simavr/cores/sim_mega1281.c
+++ b/simavr/cores/sim_mega1281.c
@@ -461,24 +461,7 @@ const struct mcu_t {
                        .vector = TIMER3_CAPT_vect,
                },
        },
-       .spi = {
-               .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-
+       AVR_SPI_DECLARE(PRR0, PRSPI),
        .twi = {
 
                .r_twcr = TWCR,

diff --git a/simavr/cores/sim_mega128rfr2.c b/simavr/cores/sim_mega128rfr2.c
index 2b0aab2265ccfdc35b80378b5efdf4fdf5faae18..ffd9ad3e5879d11d687ac820833598158b83124a 100644 (file)
--- a/simavr/cores/sim_mega128rfr2.c
+++ b/simavr/cores/sim_mega128rfr2.c
@@ -494,24 +494,7 @@ const struct mcu_t {
                        .vector = TIMER3_CAPT_vect,
                },
        },
-       .spi = {
-               .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-
+       AVR_SPI_DECLARE(PRR0, PRSPI),
        .twi = {
 
                .r_twcr = TWCR,

diff --git a/simavr/cores/sim_mega169.c b/simavr/cores/sim_mega169.c
index 93cb72b08820d6f355194af1bea817a61914e79b..41ee2aaa14ba538bf877465b9f19da4cb1e7dc4d 100644 (file)
--- a/simavr/cores/sim_mega169.c
+++ b/simavr/cores/sim_mega169.c
@@ -319,24 +319,7 @@ const struct mcu_t {
                        },
                },
        },
-       .spi = {
-               .disabled = AVR_IO_REGBIT(PRR,PRSPI),
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-
+       AVR_SPI_DECLARE(PRR, PRSPI),
 };
 
 static avr_t * make()

diff --git a/simavr/cores/sim_mega2560.c b/simavr/cores/sim_mega2560.c
index 4455bfe522ceca2fac4755e4c45544e06cb38aef..12d0645eb3ac12b98dd65a3664731516558265b8 100644 (file)
--- a/simavr/cores/sim_mega2560.c
+++ b/simavr/cores/sim_mega2560.c
@@ -718,24 +718,7 @@ const struct mcu_t {
                },
 
        },
-       .spi = {
-               .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                        .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                        .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                        .vector = SPI_STC_vect,
-               },
-       },
-
+       AVR_SPI_DECLARE(PRR0, PRSPI),
        .twi = {
 
                .r_twcr = TWCR,

diff --git a/simavr/cores/sim_megax.h b/simavr/cores/sim_megax.h
index 7d4379dd19da034b4160f31988fa2f5588155799..e2b00bf0e071846682edca973773f96c44425605 100644 (file)
--- a/simavr/cores/sim_megax.h
+++ b/simavr/cores/sim_megax.h
@@ -288,23 +288,7 @@ const struct mcu_t SIM_CORENAME = {
                        },
                },
        },
-       .spi = {
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-       
+       AVR_SPI_DECLARE(0, 0),
        .twi = {
 
                .r_twcr = TWCR,

diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index a82fd3a78fbf6682c5848d7646e13e806705f4ae..e5790245f5f75d8247d44bfee124e597b8679ba6 100644 (file)
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -462,24 +462,7 @@ const struct mcu_t SIM_CORENAME = {
                }
        },
 #endif
-       .spi = {
-               .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-       
+       AVR_SPI_DECLARE(PRR0, PRSPI),
        .twi = {
                .disabled = AVR_IO_REGBIT(PRR0,PRTWI),
 

diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index a1b2562fa253e3c151ab89672a20e58064ccad1f..28d4def384502d915a59d71a1896dbc140cd034a 100644 (file)
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -336,24 +336,7 @@ const struct mcu_t SIM_CORENAME = {
                        }
                }
        },
-       .spi = {
-               .disabled = AVR_IO_REGBIT(PRR,PRSPI),
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-
+       AVR_SPI_DECLARE(PRR, PRSPI),
        .twi = {
                .disabled = AVR_IO_REGBIT(PRR,PRTWI),
 

diff --git a/simavr/cores/sim_megaxm1.h b/simavr/cores/sim_megaxm1.h
index 46c72fb98c4bd692f3b63c129174280b1d848941..fdb929d7947fd8123637c1978bd3d532da05961c 100644 (file)
--- a/simavr/cores/sim_megaxm1.h
+++ b/simavr/cores/sim_megaxm1.h
@@ -294,24 +294,7 @@ const struct mcu_t SIM_CORENAME = {
                        },
                },
        },
-       .spi = {
-               .disabled = AVR_IO_REGBIT(PRR,PRSPI),
-
-               .r_spdr = SPDR,
-               .r_spcr = SPCR,
-               .r_spsr = SPSR,
-
-               .spe = AVR_IO_REGBIT(SPCR, SPE),
-               .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
-               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
-               .spi = {
-                       .enable = AVR_IO_REGBIT(SPCR, SPIE),
-                       .raised = AVR_IO_REGBIT(SPSR, SPIF),
-                       .vector = SPI_STC_vect,
-               },
-       },
-
+       AVR_SPI_DECLARE(PRR, PRSPI),
 };
 #endif /* SIM_CORENAME */
 

diff --git a/simavr/sim/avr_spi.h b/simavr/sim/avr_spi.h
index 0f102521bd1fea8639747b6f85eab6ef8938bb2c..79a1340f1113d6de482ef4dfa5358563e234725a 100644 (file)
--- a/simavr/sim/avr_spi.h
+++ b/simavr/sim/avr_spi.h
@@ -57,6 +57,25 @@ typedef struct avr_spi_t {
 
 void avr_spi_init(avr_t * avr, avr_spi_t * port);
 
+#define AVR_SPI_DECLARE(_prr, _prspi) \
+       .spi = { \
+               .disabled = AVR_IO_REGBIT(_prr, _prspi), \
+       \
+               .r_spdr = SPDR, \
+               .r_spcr = SPCR, \
+               .r_spsr = SPSR, \
+       \
+               .spe = AVR_IO_REGBIT(SPCR, SPE), \
+               .mstr = AVR_IO_REGBIT(SPCR, MSTR), \
+       \
+               .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) }, \
+               .spi = { \
+                       .enable = AVR_IO_REGBIT(SPCR, SPIE), \
+                       .raised = AVR_IO_REGBIT(SPSR, SPIF), \
+                       .vector = SPI_STC_vect, \
+               }, \
+       }
+
 #ifdef __cplusplus
 };
 #endif