e58a4c12191abd3b910e34842ada9b23590a708b

From about 1GHz to 100MHz. Shouldn't have an impact on simavr proper,
but might help with Pulseview

Signed-off-by: Michel Pollet <buserror@gmail.com>

diff --git a/simavr/sim/sim_vcd_file.c b/simavr/sim/sim_vcd_file.c
index f0d80be607aaeb103e00790e37135735fa8f68c6..246ae7c6f25b1390952788529f283bac5fcc6da7 100644 (file)
--- a/simavr/sim/sim_vcd_file.c
+++ b/simavr/sim/sim_vcd_file.c
@@ -398,8 +398,8 @@ avr_vcd_flush_log(
 
        while (!avr_vcd_fifo_isempty(&vcd->log)) {
                avr_vcd_log_t l = avr_vcd_fifo_read(&vcd->log);
-               // 1ns base
-               uint64_t base = avr_cycles_to_nsec(vcd->avr, l.when - vcd->start);
+               // 10ns base -- 100MHz should be enough
+               uint64_t base = avr_cycles_to_nsec(vcd->avr, l.when - vcd->start) / 10;
 
                /*
                 * if that trace was seen in this nsec already, we fudge the
@@ -525,7 +525,7 @@ avr_vcd_start(
                return -1;
        }
 
-       fprintf(vcd->output, "$timescale 1ns $end\n");  // 1ns base
+       fprintf(vcd->output, "$timescale 10ns $end\n"); // 10ns base, aka 100MHz
        fprintf(vcd->output, "$scope module logic $end\n");
 
        for (int i = 0; i < vcd->signal_count; i++) {