--- /dev/null
+/*
+ sim_90usb162.c
+
+ Copyright 2012 Torbjorn Tyridal <ttyridal@gmail.com>
+
+ This file is part of simavr.
+
+ simavr is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ simavr is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with simavr. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include "sim_avr.h"
+#include "sim_core_declare.h"
+#include "avr_eeprom.h"
+#include "avr_flash.h"
+#include "avr_watchdog.h"
+#include "avr_extint.h"
+#include "avr_ioport.h"
+#include "avr_uart.h"
+#include "avr_adc.h"
+#include "avr_timer.h"
+#include "avr_spi.h"
+#include "avr_usb.h"
+
+void usb162_init(struct avr_t * avr);
+void usb162_reset(struct avr_t * avr);
+
+#define _AVR_IO_H_
+#define __ASSEMBLER__
+#include "avr/iousb162.h"
+
+struct mcu_t {
+ avr_t core;
+ avr_eeprom_t eeprom;
+ avr_flash_t selfprog;
+ avr_watchdog_t watchdog;
+ avr_extint_t extint;
+ avr_ioport_t portb, portc, portd;
+ avr_uart_t uart1;
+ avr_timer_t timer0,timer1;
+ avr_spi_t spi;
+ avr_usb_t usb;
+} mcu_usb162 = {
+ .core = {
+ .mmcu = "at90usb162",
+ DEFAULT_CORE(4),
+
+ .init = usb162_init,
+ .reset = usb162_reset,
+ },
+ AVR_EEPROM_DECLARE(EE_READY_vect),
+ AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
+ AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
+ .extint = {
+ AVR_EXTINT_DECLARE(0, 'D', PD0),
+ AVR_EXTINT_DECLARE(1, 'D', PD1),
+ AVR_EXTINT_DECLARE(2, 'D', PD2),
+ AVR_EXTINT_DECLARE(3, 'D', PD3),
+ AVR_EXTINT_DECLARE(4, 'C', PC7),
+ AVR_EXTINT_DECLARE(5, 'D', PD4),
+ AVR_EXTINT_DECLARE(6, 'D', PD6),
+ AVR_EXTINT_DECLARE(7, 'D', PD7),
+ },
+ .portb = {
+ .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
+ .pcint = {
+ .enable = AVR_IO_REGBIT(PCICR, PCIE0),
+ .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
+ .vector = PCINT0_vect,
+ },
+ .r_pcint = PCMSK0,
+ },
+ .portc = {
+ .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
+ .pcint = {
+ .enable = AVR_IO_REGBIT(PCICR, PCIE1),
+ .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
+ .vector = PCINT1_vect,
+ },
+ .r_pcint = PCMSK1,
+ },
+ .portd = {
+ .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
+ },
+
+ .uart1 = {
+ .disabled = AVR_IO_REGBIT(PRR1,PRUSART1),
+ .name = '1',
+ .r_udr = UDR1,
+
+ .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
+ .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
+ .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
+ .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), // 1 bits
+
+ .r_ucsra = UCSR1A,
+ .r_ucsrb = UCSR1B,
+ .r_ucsrc = UCSR1C,
+ .r_ubrrl = UBRR1L,
+ .r_ubrrh = UBRR1H,
+ .rxc = {
+ .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
+ .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
+ .vector = USART1_RX_vect,
+ },
+ .txc = {
+ .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
+ .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
+ .vector = USART1_TX_vect,
+ },
+ .udrc = {
+ .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
+ .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
+ .vector = USART1_UDRE_vect,
+ },
+ },
+ .timer0 = {
+ .name = '0',
+ .disabled = AVR_IO_REGBIT(PRR0,PRTIM0),
+ .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
+ .wgm_op = {
+ [0] = AVR_TIMER_WGM_NORMAL8(),
+ [2] = AVR_TIMER_WGM_CTC(),
+ [3] = AVR_TIMER_WGM_FASTPWM8(),
+ [7] = AVR_TIMER_WGM_OCPWM(),
+ },
+ .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
+ .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
+
+ .r_tcnt = TCNT0,
+
+ .overflow = {
+ .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
+ .raised = AVR_IO_REGBIT(TIFR0, TOV0),
+ .vector = TIMER0_OVF_vect,
+ },
+ .comp = {
+ [AVR_TIMER_COMPA] = {
+ .r_ocr = OCR0A,
+ .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTD, 6),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
+ .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
+ .vector = TIMER0_COMPA_vect,
+ },
+ },
+ [AVR_TIMER_COMPB] = {
+ .r_ocr = OCR0B,
+ .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTD, 5),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
+ .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
+ .vector = TIMER0_COMPB_vect,
+ }
+ }
+ }
+ },
+ .timer1 = {
+ .name = '1',
+ .disabled = AVR_IO_REGBIT(PRR0,PRTIM1),
+ .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
+ AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
+ .wgm_op = {
+ [0] = AVR_TIMER_WGM_NORMAL16(),
+ [4] = AVR_TIMER_WGM_CTC(),
+ [5] = AVR_TIMER_WGM_FASTPWM8(),
+ [6] = AVR_TIMER_WGM_FASTPWM9(),
+ [7] = AVR_TIMER_WGM_FASTPWM10(),
+ [12] = AVR_TIMER_WGM_ICCTC(),
+ [14] = AVR_TIMER_WGM_ICPWM(),
+ [15] = AVR_TIMER_WGM_OCPWM(),
+ },
+ .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
+ .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
+
+ .r_tcnt = TCNT1L,
+ .r_tcnth = TCNT1H,
+ .r_icr = ICR1L,
+ .r_icrh = ICR1H,
+
+ .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
+ .icp = AVR_IO_REGBIT(PORTB, 0),
+
+ .overflow = {
+ .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
+ .raised = AVR_IO_REGBIT(TIFR1, TOV1),
+ .vector = TIMER1_OVF_vect,
+ },
+ .icr = {
+ .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
+ .raised = AVR_IO_REGBIT(TIFR1, ICF1),
+ .vector = TIMER1_CAPT_vect,
+ },
+ .comp = {
+ [AVR_TIMER_COMPA] = {
+ .r_ocr = OCR1AL,
+ .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
+ .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, 1),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
+ .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
+ .vector = TIMER1_COMPA_vect,
+ },
+ },
+ [AVR_TIMER_COMPB] = {
+ .r_ocr = OCR1BL,
+ .r_ocrh = OCR1BH,
+ .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
+ .com_pin = AVR_IO_REGBIT(PORTB, 2),
+ .interrupt = {
+ .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
+ .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
+ .vector = TIMER1_COMPB_vect,
+ },
+ },
+ },
+ },
+ .spi = {
+
+ .r_spdr = SPDR,
+ .r_spcr = SPCR,
+ .r_spsr = SPSR,
+
+ .spe = AVR_IO_REGBIT(SPCR, SPE),
+ .mstr = AVR_IO_REGBIT(SPCR, MSTR),
+
+ .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
+ .spi = {
+ .enable = AVR_IO_REGBIT(SPCR, SPIE),
+ .raised = AVR_IO_REGBIT(SPSR, SPIF),
+ .vector = SPI_STC_vect,
+ },
+ },
+ .usb = {
+ .name='1',
+ .disabled=AVR_IO_REGBIT(PRR1, PRUSB),// bit in the PRR
+
+ .usbrf=AVR_IO_REGBIT(MCUSR,USBRF), // bit in the MCUSR
+
+ .r_usbcon = USBCON,
+ .r_pllcsr=PLLCSR,
+
+ .usb_com_vect=USB_COM_vect,
+ .usb_gen_vect=USB_GEN_vect,
+ },
+};
+
+static avr_t * make()
+{
+ return &mcu_usb162.core;
+}
+
+avr_kind_t usb162 = {
+ .names = { "at90usb162" },
+ .make = make
+};
+
+void usb162_init(struct avr_t * avr)
+{
+ struct mcu_t * mcu = (struct mcu_t*)avr;
+
+ printf("%s init\n", avr->mmcu);
+
+ avr_eeprom_init(avr, &mcu->eeprom);
+ avr_flash_init(avr, &mcu->selfprog);
+ avr_extint_init(avr, &mcu->extint);
+ avr_watchdog_init(avr, &mcu->watchdog);
+ avr_ioport_init(avr, &mcu->portb);
+ avr_ioport_init(avr, &mcu->portc);
+ avr_ioport_init(avr, &mcu->portd);
+ avr_uart_init(avr, &mcu->uart1);
+ avr_timer_init(avr, &mcu->timer0);
+ avr_timer_init(avr, &mcu->timer1);
+ avr_spi_init(avr, &mcu->spi);
+ avr_usb_init(avr, &mcu->usb);
+}
+
+void usb162_reset(struct avr_t * avr)
+{
+// struct mcu_t * mcu = (struct mcu_t*)avr;
+}
projects / sx / simavr.git / commitdiff