From: Michel Pollet <buserror@gmail.com>
Date: Sat, 10 Apr 2010 12:18:30 +0000 (+0100)
Subject: cores: Refactored timer comparators
X-Git-Tag: v1.0a2~7
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=12785a574be48f05786975caf6a3860b04b65575;p=sx%2Fsimavr.git

cores: Refactored timer comparators

Based on patch by <tomi.leppikangas@gmail.com> but fixed the other
cores to fix a few cut/paste issues.

Signed-off-by: Michel Pollet <buserror@gmail.com>
---

diff --git a/simavr/cores/sim_mega128.c b/simavr/cores/sim_mega128.c
index 90765f0..8b617cd 100644
--- a/simavr/cores/sim_mega128.c
+++ b/simavr/cores/sim_mega128.c
@@ -199,7 +199,6 @@ struct mcu_t {
 		// asynchronous timer source bit.. if set, use 32khz frequency
 		.as2 = AVR_IO_REGBIT(ASSR, AS0),
 		
-		.r_ocra = OCR0,
 		.r_tcnt = TCNT0,
 
 		.overflow = {
@@ -207,10 +206,15 @@ struct mcu_t {
 			.raised = AVR_IO_REGBIT(TIFR, TOV0),
 			.vector = TIMER0_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE0),
-			.raised = AVR_IO_REGBIT(TIFR, OCF0),
-			.vector = TIMER0_COMP_vect,
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR0,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE0),
+					.raised = AVR_IO_REGBIT(TIFR, OCF0),
+					.vector = TIMER0_COMP_vect,
+				},
+			},
 		},
 	},
 	.timer1 = {
@@ -234,15 +238,9 @@ struct mcu_t {
 		.cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* TODO: 2 External clocks */},
 
-		.r_ocra = OCR1AL,
-		.r_ocrb = OCR1BL,
-		.r_ocrc = OCR1CL,
 		.r_tcnt = TCNT1L,
 		.r_icr = ICR1L,
 		.r_icrh = ICR1H,
-		.r_ocrah = OCR1AH,	// 16 bits timers have two bytes of it
-		.r_ocrbh = OCR1BH,
-		.r_ocrch = OCR1CH,
 		.r_tcnth = TCNT1H,
 
 		.overflow = {
@@ -250,26 +248,41 @@ struct mcu_t {
 			.raised = AVR_IO_REGBIT(TIFR, TOV1),
 			.vector = TIMER1_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
-			.raised = AVR_IO_REGBIT(TIFR, OCF1A),
-			.vector = TIMER1_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
-			.raised = AVR_IO_REGBIT(TIFR, OCF1B),
-			.vector = TIMER1_COMPB_vect,
-		},
-		.compc = {
-			.enable = AVR_IO_REGBIT(ETIMSK, OCIE1C),
-			.raised = AVR_IO_REGBIT(ETIFR, OCF1C),
-			.vector = TIMER1_COMPC_vect,
-		},
 		.icr = {
 			.enable = AVR_IO_REGBIT(TIMSK, TICIE1),
 			.raised = AVR_IO_REGBIT(TIFR, ICF1),
 			.vector = TIMER1_CAPT_vect,
 		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR1AL,
+				.r_ocrh = OCR1AH,	// 16 bits timers have two bytes of it
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
+					.raised = AVR_IO_REGBIT(TIFR, OCF1A),
+					.vector = TIMER1_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR1BL,
+				.r_ocrh = OCR1BH,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
+					.raised = AVR_IO_REGBIT(TIFR, OCF1B),
+					.vector = TIMER1_COMPB_vect,
+				},
+			},
+			[AVR_TIMER_COMPC] = {
+				.r_ocr = OCR1CL,
+				.r_ocrh = OCR1CH,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(ETIMSK, OCIE1C),
+					.raised = AVR_IO_REGBIT(ETIFR, OCF1C),
+					.vector = TIMER1_COMPC_vect,
+				},
+			},
+		},
+
 	},
 	.timer2 = {
 		.name = '2',
@@ -283,7 +296,6 @@ struct mcu_t {
 		.cs = { AVR_IO_REGBIT(TCCR2, CS20), AVR_IO_REGBIT(TCCR2, CS21), AVR_IO_REGBIT(TCCR2, CS22) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO external clock */ },
 
-		.r_ocra = OCR2,
 		.r_tcnt = TCNT2,
 		
 		.overflow = {
@@ -291,10 +303,15 @@ struct mcu_t {
 			.raised = AVR_IO_REGBIT(TIFR, TOV2),
 			.vector = TIMER2_OVF_vect,
 		},
-		.compa = {  // compa is just COMP
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE2),
-			.raised = AVR_IO_REGBIT(TIFR, OCF2),
-			.vector = TIMER2_COMP_vect,
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR2,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE2),
+					.raised = AVR_IO_REGBIT(TIFR, OCF2),
+					.vector = TIMER2_COMP_vect,
+				},
+			},
 		},
 	},
 	.timer3 = {
@@ -321,15 +338,9 @@ struct mcu_t {
 		.cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* TODO: 2 External clocks */},
 
-		.r_ocra = OCR3AL,
-		.r_ocrb = OCR3BL,
-		.r_ocrc = OCR3CL,
 		.r_tcnt = TCNT3L,
 		.r_icr = ICR3L,
 		.r_icrh = ICR3H,
-		.r_ocrah = OCR3AH,	// 16 bits timers have two bytes of it
-		.r_ocrbh = OCR3BH,
-		.r_ocrch = OCR3CH,
 		.r_tcnth = TCNT3H,
 
 		.overflow = {
@@ -337,20 +348,40 @@ struct mcu_t {
 			.raised = AVR_IO_REGBIT(ETIFR, TOV3),
 			.vector = TIMER3_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(ETIMSK, OCIE3A),
-			.raised = AVR_IO_REGBIT(ETIFR, OCF3A),
-			.vector = TIMER3_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(ETIMSK, OCIE3B),
-			.raised = AVR_IO_REGBIT(ETIFR, OCF3B),
-			.vector = TIMER3_COMPB_vect,
-		},
-		.compc = {
-			.enable = AVR_IO_REGBIT(ETIMSK, OCIE3C),
-			.raised = AVR_IO_REGBIT(ETIFR, OCF3C),
-			.vector = TIMER3_COMPC_vect,
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR3AL,
+				.r_ocrh = OCR3AH,	// 16 bits timers have two bytes of it
+				.com = { AVR_IO_REGBIT(TCCR3A, COM3A1), AVR_IO_REGBIT(TCCR3A, COM3A0) },
+				.com_pin = AVR_IO_REGBIT(PORTE, PE3),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(ETIMSK, OCIE3A),
+					.raised = AVR_IO_REGBIT(ETIFR, OCF3A),
+					.vector = TIMER3_COMPA_vect,
+				}
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR3BL,
+				.r_ocrh = OCR3BH,
+				.com = { AVR_IO_REGBIT(TCCR3A, COM3B1), AVR_IO_REGBIT(TCCR3A, COM3B0) },
+				.com_pin = AVR_IO_REGBIT(PORTE, PE4),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(ETIMSK, OCIE3B),
+					.raised = AVR_IO_REGBIT(ETIFR, OCF3B),
+					.vector = TIMER3_COMPB_vect,
+				}
+			},
+			[AVR_TIMER_COMPC] = {
+				.r_ocr = OCR3CL,
+				.r_ocrh = OCR3CH,
+				.com = { AVR_IO_REGBIT(TCCR3A, COM3C1), AVR_IO_REGBIT(TCCR3A, COM3C0) },
+				.com_pin = AVR_IO_REGBIT(PORTE, PE5),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(ETIMSK, OCIE3C),
+					.raised = AVR_IO_REGBIT(ETIFR, OCF3C),
+					.vector = TIMER3_COMPC_vect,
+				}
+			}
 		},
 		.icr = {
 			.enable = AVR_IO_REGBIT(ETIMSK, TICIE3),
diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index 0193389..7af0bc6 100644
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -209,8 +209,6 @@ struct mcu_t SIM_CORENAME = {
 		.cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
-		.r_ocra = OCR0A,
-		.r_ocrb = OCR0B,
 		.r_tcnt = TCNT0,
 
 		.overflow = {
@@ -218,16 +216,24 @@ struct mcu_t SIM_CORENAME = {
 			.raised = AVR_IO_REGBIT(TIFR0, TOV0),
 			.vector = TIMER0_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
-			.raised = AVR_IO_REGBIT(TIFR0, OCF0A),
-			.vector = TIMER0_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
-			.raised = AVR_IO_REGBIT(TIFR0, OCF0B),
-			.vector = TIMER0_COMPB_vect,
-		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR0A,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
+					.raised = AVR_IO_REGBIT(TIFR0, OCF0A),
+					.vector = TIMER0_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR0B,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
+					.raised = AVR_IO_REGBIT(TIFR0, OCF0B),
+					.vector = TIMER0_COMPB_vect,
+				}
+			}
+		}
 	},
 	.timer1 = {
 		.name = '1',
@@ -247,13 +253,9 @@ struct mcu_t SIM_CORENAME = {
 		.cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 
-		.r_ocra = OCR1AL,
-		.r_ocrb = OCR1BL,
 		.r_tcnt = TCNT1L,
 		.r_icr = ICR1L,
 		.r_icrh = ICR1H,
-		.r_ocrah = OCR1AH,	// 16 bits timers have two bytes of it
-		.r_ocrbh = OCR1BH,
 		.r_tcnth = TCNT1H,
 
 		.overflow = {
@@ -261,21 +263,31 @@ struct mcu_t SIM_CORENAME = {
 			.raised = AVR_IO_REGBIT(TIFR1, TOV1),
 			.vector = TIMER1_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
-			.raised = AVR_IO_REGBIT(TIFR1, OCF1A),
-			.vector = TIMER1_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
-			.raised = AVR_IO_REGBIT(TIFR1, OCF1B),
-			.vector = TIMER1_COMPB_vect,
-		},
 		.icr = {
 			.enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
 			.raised = AVR_IO_REGBIT(TIFR1, ICF1),
 			.vector = TIMER1_CAPT_vect,
 		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR1AL,
+				.r_ocrh = OCR1AH,	// 16 bits timers have two bytes of it
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
+					.raised = AVR_IO_REGBIT(TIFR1, OCF1A),
+					.vector = TIMER1_COMPA_vect,
+				}
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR1BL,
+				.r_ocrh = OCR1BH,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
+					.raised = AVR_IO_REGBIT(TIFR1, OCF1B),
+					.vector = TIMER1_COMPB_vect,
+				}
+			}
+		}
 	},
 	.timer2 = {
 		.name = '2',
@@ -289,8 +301,6 @@ struct mcu_t SIM_CORENAME = {
 		.cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
 		.cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
 
-		.r_ocra = OCR2A,
-		.r_ocrb = OCR2B,
 		.r_tcnt = TCNT2,
 		
 		// asynchronous timer source bit.. if set, use 32khz frequency
@@ -301,16 +311,24 @@ struct mcu_t SIM_CORENAME = {
 			.raised = AVR_IO_REGBIT(TIFR2, TOV2),
 			.vector = TIMER2_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
-			.raised = AVR_IO_REGBIT(TIFR2, OCF2A),
-			.vector = TIMER2_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
-			.raised = AVR_IO_REGBIT(TIFR2, OCF2B),
-			.vector = TIMER2_COMPB_vect,
-		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR2A,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
+					.raised = AVR_IO_REGBIT(TIFR2, OCF2A),
+					.vector = TIMER2_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR2B,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
+					.raised = AVR_IO_REGBIT(TIFR2, OCF2B),
+					.vector = TIMER2_COMPB_vect,
+				},
+			}
+		}
 	},
 	.spi = {
 		.disabled = AVR_IO_REGBIT(PRR,PRSPI),
diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index 936af57..4e153de 100644
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -173,8 +173,6 @@ struct mcu_t SIM_CORENAME = {
 		.cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
-		.r_ocra = OCR0A,
-		.r_ocrb = OCR0B,
 		.r_tcnt = TCNT0,
 
 		.overflow = {
@@ -182,16 +180,28 @@ struct mcu_t SIM_CORENAME = {
 			.raised = AVR_IO_REGBIT(TIFR0, TOV0),
 			.vector = TIMER0_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
-			.raised = AVR_IO_REGBIT(TIFR0, OCF0A),
-			.vector = TIMER0_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
-			.raised = AVR_IO_REGBIT(TIFR0, OCF0B),
-			.vector = TIMER0_COMPB_vect,
-		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR0A,
+				.com = { AVR_IO_REGBIT(TCCR0A, COM0A0), AVR_IO_REGBIT(TCCR0A, COM0A1) },
+				.com_pin = AVR_IO_REGBIT(PORTD, 6),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
+					.raised = AVR_IO_REGBIT(TIFR0, OCF0A),
+					.vector = TIMER0_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR0B,
+				.com = { AVR_IO_REGBIT(TCCR0A, COM0B0), AVR_IO_REGBIT(TCCR0A, COM0B1) },
+				.com_pin = AVR_IO_REGBIT(PORTD, 5),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
+					.raised = AVR_IO_REGBIT(TIFR0, OCF0B),
+					.vector = TIMER0_COMPB_vect,
+				}
+			}
+		}
 	},
 	.timer1 = {
 		.name = '1',
@@ -211,13 +221,9 @@ struct mcu_t SIM_CORENAME = {
 		.cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 
-		.r_ocra = OCR1AL,
-		.r_ocrb = OCR1BL,
 		.r_tcnt = TCNT1L,
 		.r_icr = ICR1L,
 		.r_icrh = ICR1H,
-		.r_ocrah = OCR1AH,	// 16 bits timers have two bytes of it
-		.r_ocrbh = OCR1BH,
 		.r_tcnth = TCNT1H,
 
 		.overflow = {
@@ -225,21 +231,35 @@ struct mcu_t SIM_CORENAME = {
 			.raised = AVR_IO_REGBIT(TIFR1, TOV1),
 			.vector = TIMER1_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
-			.raised = AVR_IO_REGBIT(TIFR1, OCF1A),
-			.vector = TIMER1_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
-			.raised = AVR_IO_REGBIT(TIFR1, OCF1B),
-			.vector = TIMER1_COMPB_vect,
-		},
 		.icr = {
 			.enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
 			.raised = AVR_IO_REGBIT(TIFR1, ICF1),
 			.vector = TIMER1_CAPT_vect,
 		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR1AL,
+				.r_ocrh = OCR1AH,	// 16 bits timers have two bytes of it
+				.com = { AVR_IO_REGBIT(TCCR1A, COM1A0), AVR_IO_REGBIT(TCCR1A, COM1A1) },
+				.com_pin = AVR_IO_REGBIT(PORTB, 1),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
+					.raised = AVR_IO_REGBIT(TIFR1, OCF1A),
+					.vector = TIMER1_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR1BL,
+				.r_ocrh = OCR1BH,
+				.com = { AVR_IO_REGBIT(TCCR1A, COM1B0), AVR_IO_REGBIT(TCCR1A, COM1B1) },
+				.com_pin = AVR_IO_REGBIT(PORTB, 2),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
+					.raised = AVR_IO_REGBIT(TIFR1, OCF1B),
+					.vector = TIMER1_COMPB_vect,
+				},
+			},
+		},
 	},
 	.timer2 = {
 		.name = '2',
@@ -255,8 +275,6 @@ struct mcu_t SIM_CORENAME = {
 		.cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
 		.cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
 
-		.r_ocra = OCR2A,
-		.r_ocrb = OCR2B,
 		.r_tcnt = TCNT2,
 		
 		// asynchronous timer source bit.. if set, use 32khz frequency
@@ -267,18 +285,29 @@ struct mcu_t SIM_CORENAME = {
 			.raised = AVR_IO_REGBIT(TIFR2, TOV2),
 			.vector = TIMER2_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
-			.raised = AVR_IO_REGBIT(TIFR2, OCF2A),
-			.vector = TIMER2_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
-			.raised = AVR_IO_REGBIT(TIFR2, OCF2B),
-			.vector = TIMER2_COMPB_vect,
-		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR2A,
+				.com = { AVR_IO_REGBIT(TCCR2A, COM2A0), AVR_IO_REGBIT(TCCR2A, COM2A1) },
+				.com_pin = AVR_IO_REGBIT(PORTB, 3),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
+					.raised = AVR_IO_REGBIT(TIFR2, OCF2A),
+					.vector = TIMER2_COMPA_vect,
+				}
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR2B,
+				.com = { AVR_IO_REGBIT(TCCR2A, COM2B0), AVR_IO_REGBIT(TCCR2A, COM2B1) },
+				.com_pin = AVR_IO_REGBIT(PORTD, 3),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
+					.raised = AVR_IO_REGBIT(TIFR2, OCF2B),
+					.vector = TIMER2_COMPB_vect,
+				}
+			}
+		}
 	},
-	
 	.spi = {
 		.disabled = AVR_IO_REGBIT(PRR,PRSPI),
 
diff --git a/simavr/cores/sim_tiny13.c b/simavr/cores/sim_tiny13.c
index b14c300..99587ce 100644
--- a/simavr/cores/sim_tiny13.c
+++ b/simavr/cores/sim_tiny13.c
@@ -92,8 +92,6 @@ static struct mcu_t {
 		.cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
-		.r_ocra = OCR0A,
-		.r_ocrb = OCR0B,
 		.r_tcnt = TCNT0,
 
 		.overflow = {
@@ -101,17 +99,25 @@ static struct mcu_t {
 			.raised = AVR_IO_REGBIT(TIFR0, TOV0),
 			.vector = TIM0_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
-			.raised = AVR_IO_REGBIT(TIFR0, OCF0A),
-			.vector = TIM0_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
-			.raised = AVR_IO_REGBIT(TIFR0, OCF0B),
-			.vector = TIM0_COMPB_vect,
-		},
-	},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR0A,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
+					.raised = AVR_IO_REGBIT(TIFR0, OCF0A),
+					.vector = TIM0_COMPA_vect,
+				}
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR0B,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
+					.raised = AVR_IO_REGBIT(TIFR0, OCF0B),
+					.vector = TIM0_COMPB_vect,
+				}
+			}
+		}
+	}
 };
 
 static avr_t * make()
diff --git a/simavr/cores/sim_tiny2313.c b/simavr/cores/sim_tiny2313.c
index 1a58de4..9ef4434 100644
--- a/simavr/cores/sim_tiny2313.c
+++ b/simavr/cores/sim_tiny2313.c
@@ -114,8 +114,6 @@ static struct mcu_t {
 		.cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
-		.r_ocra = OCR0A,
-		.r_ocrb = OCR0B,
 		.r_tcnt = TCNT0,
 
 		.overflow = {
@@ -123,15 +121,23 @@ static struct mcu_t {
 			.raised = AVR_IO_REGBIT(TIFR, TOV0),
 			.vector = TIMER0_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
-			.raised = AVR_IO_REGBIT(TIFR, OCF0A),
-			.vector = TIMER0_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
-			.raised = AVR_IO_REGBIT(TIFR, OCF0B),
-			.vector = TIMER0_COMPB_vect,
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR0A,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
+					.raised = AVR_IO_REGBIT(TIFR, OCF0A),
+					.vector = TIMER0_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR0B,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
+					.raised = AVR_IO_REGBIT(TIFR, OCF0B),
+					.vector = TIMER0_COMPB_vect,
+				}
+			}
 		},
 	},
 	.timer1 = {
@@ -152,13 +158,9 @@ static struct mcu_t {
 		.cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 
-		.r_ocra = OCR1AL,
-		.r_ocrb = OCR1BL,
 		.r_tcnt = TCNT1L,
 		.r_icr = ICR1L,
 		.r_icrh = ICR1H,
-		.r_ocrah = OCR1AH,	// 16 bits timers have two bytes of it
-		.r_ocrbh = OCR1BH,
 		.r_tcnth = TCNT1H,
 
 		.overflow = {
@@ -166,22 +168,32 @@ static struct mcu_t {
 			.raised = AVR_IO_REGBIT(TIFR, TOV1),
 			.vector = TIMER1_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
-			.raised = AVR_IO_REGBIT(TIFR, OCF1A),
-			.vector = TIMER1_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
-			.raised = AVR_IO_REGBIT(TIFR, OCF1B),
-			.vector = TIMER1_COMPB_vect,
-		},
 		.icr = {
 			.enable = AVR_IO_REGBIT(TIMSK, ICIE1),
 			.raised = AVR_IO_REGBIT(TIFR, ICF1),
 			.vector = TIMER1_CAPT_vect,
 		},
-	},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR1AL,
+				.r_ocrh = OCR1AH,	// 16 bits timers have two bytes of it
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
+					.raised = AVR_IO_REGBIT(TIFR, OCF1A),
+					.vector = TIMER1_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR1BL,
+				.r_ocrh = OCR1BH,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
+					.raised = AVR_IO_REGBIT(TIFR, OCF1B),
+					.vector = TIMER1_COMPB_vect,
+				}
+			}
+		}
+	}
 };
 
 static avr_t * make()
diff --git a/simavr/cores/sim_tinyx5.h b/simavr/cores/sim_tinyx5.h
index 27e5688..60c323d 100644
--- a/simavr/cores/sim_tinyx5.h
+++ b/simavr/cores/sim_tinyx5.h
@@ -117,8 +117,6 @@ struct mcu_t SIM_CORENAME = {
 		.cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 
-		.r_ocra = OCR0A,
-		.r_ocrb = OCR0B,
 		.r_tcnt = TCNT0,
 
 		.overflow = {
@@ -126,15 +124,23 @@ struct mcu_t SIM_CORENAME = {
 			.raised = AVR_IO_REGBIT(TIFR, TOV0),
 			.vector = TIMER0_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
-			.raised = AVR_IO_REGBIT(TIFR, OCF0A),
-			.vector = TIMER0_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
-			.raised = AVR_IO_REGBIT(TIFR, OCF0B),
-			.vector = TIMER0_COMPB_vect,
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR0A,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
+					.raised = AVR_IO_REGBIT(TIFR, OCF0A),
+					.vector = TIMER0_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR0B,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
+					.raised = AVR_IO_REGBIT(TIFR, OCF0B),
+					.vector = TIMER0_COMPB_vect,
+				},
+			},
 		},
 	},
 	.timer1 = {
@@ -143,9 +149,6 @@ struct mcu_t SIM_CORENAME = {
 		.cs = { AVR_IO_REGBIT(TCCR1, CS10), AVR_IO_REGBIT(TCCR1, CS11), AVR_IO_REGBIT(TCCR1, CS12), AVR_IO_REGBIT(TCCR1, CS13) },
 		.cs_div = { 0, 0, 1 /* 2 */, 2 /* 4 */, 3 /* 8 */, 4 /* 16 */ },
 
-		.r_ocra = OCR1A,
-		.r_ocrb = OCR1B,
-		.r_ocrc = OCR1C,
 		.r_tcnt = TCNT1,
 
 		.overflow = {
@@ -153,19 +156,28 @@ struct mcu_t SIM_CORENAME = {
 			.raised = AVR_IO_REGBIT(TIFR, TOV1),
 			.vector = TIMER1_OVF_vect,
 		},
-		.compa = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
-			.raised = AVR_IO_REGBIT(TIFR, OCF1A),
-			.vector = TIMER1_COMPA_vect,
-		},
-		.compb = {
-			.enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
-			.raised = AVR_IO_REGBIT(TIFR, OCF1B),
-			.vector = TIMER1_COMPB_vect,
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR1A,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
+					.raised = AVR_IO_REGBIT(TIFR, OCF1A),
+					.vector = TIMER1_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR1B,
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
+					.raised = AVR_IO_REGBIT(TIFR, OCF1B),
+					.vector = TIMER1_COMPB_vect,
+				},
+			},
+			[AVR_TIMER_COMPC] = {
+				.r_ocr = OCR1C,
+			},
 		},
 	},
-
-
 };
 #endif /* SIM_CORENAME */