From: Michel Pollet <buserror@gmail.com>
Date: Thu, 17 Dec 2009 19:46:25 +0000 (+0000)
Subject: cores: Add a few more mega cores
X-Git-Tag: v1.0a1~53
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=2b3fa0405f06adcf414e4014e0da9af5d280033e;p=sx%2Fsimavr.git
cores: Add a few more mega cores
Added mega164, mega324, mega328
Signed-off-by: Michel Pollet <buserror@gmail.com>
---
diff --git a/simavr/cores/sim_mega164.c b/simavr/cores/sim_mega164.c
new file mode 100644
index 0000000..d9f2c91
--- /dev/null
+++ b/simavr/cores/sim_mega164.c
@@ -0,0 +1,42 @@
+/*
+ sim_mega164.c
+
+ Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
+
+ This file is part of simavr.
+
+ simavr is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ simavr is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with simavr. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sim_avr.h"
+
+#define SIM_MMCU "atmega164"
+#define SIM_CORENAME mcu_mega164
+
+#define _AVR_IO_H_
+#define __ASSEMBLER__
+#include "avr/iom164.h"
+// instanciate the new core
+#include "sim_megax4.h"
+
+static avr_t * make()
+{
+ return &SIM_CORENAME.core;
+}
+
+avr_kind_t mega164 = {
+ .names = { "atmega164", "atmega164p", "atmega164pa" },
+ .make = make
+};
+
diff --git a/simavr/cores/sim_mega324.c b/simavr/cores/sim_mega324.c
new file mode 100644
index 0000000..2bbebec
--- /dev/null
+++ b/simavr/cores/sim_mega324.c
@@ -0,0 +1,42 @@
+/*
+ sim_mega324.c
+
+ Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
+
+ This file is part of simavr.
+
+ simavr is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ simavr is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with simavr. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sim_avr.h"
+
+#define SIM_MMCU "atmega324"
+#define SIM_CORENAME mcu_mega324
+
+#define _AVR_IO_H_
+#define __ASSEMBLER__
+#include "avr/iom324.h"
+// instanciate the new core
+#include "sim_megax4.h"
+
+static avr_t * make()
+{
+ return &SIM_CORENAME.core;
+}
+
+avr_kind_t mega324 = {
+ .names = { "atmega324", "atmega324p", "atmega324pa" },
+ .make = make
+};
+
diff --git a/simavr/cores/sim_mega328.c b/simavr/cores/sim_mega328.c
new file mode 100644
index 0000000..3ed50d0
--- /dev/null
+++ b/simavr/cores/sim_mega328.c
@@ -0,0 +1,43 @@
+/*
+ sim_mega328.c
+
+ Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
+
+ This file is part of simavr.
+
+ simavr is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ simavr is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with simavr. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sim_avr.h"
+
+#define SIM_VECTOR_SIZE 4
+#define SIM_MMCU "atmega328"
+#define SIM_CORENAME mcu_mega328
+
+#define _AVR_IO_H_
+#define __ASSEMBLER__
+#include "avr/iom328p.h"
+// instanciate the new core
+#include "sim_megax8.h"
+
+static avr_t * make()
+{
+ return &SIM_CORENAME.core;
+}
+
+avr_kind_t mega328 = {
+ .names = { "atmega328", "atmega328p" },
+ .make = make
+};
+
diff --git a/simavr/cores/sim_mega644.c b/simavr/cores/sim_mega644.c
index 5ff5423..bc20f6e 100644
--- a/simavr/cores/sim_mega644.c
+++ b/simavr/cores/sim_mega644.c
@@ -19,248 +19,20 @@
along with simavr. If not, see <http://www.gnu.org/licenses/>.
*/
-#include </usr/include/stdio.h>
#include "sim_avr.h"
-#include "sim_core_declare.h"
-#include "avr_eeprom.h"
-#include "avr_extint.h"
-#include "avr_ioport.h"
-#include "avr_uart.h"
-#include "avr_timer8.h"
-#include "avr_spi.h"
-#include "avr_twi.h"
+
+#define SIM_MMCU "atmega644"
+#define SIM_CORENAME mcu_mega644
#define _AVR_IO_H_
#define __ASSEMBLER__
#include "avr/iom644.h"
-
-static void init(struct avr_t * avr);
-static void reset(struct avr_t * avr);
-
-
-static struct mcu_t {
- avr_t core;
- avr_eeprom_t eeprom;
- avr_extint_t extint;
- avr_ioport_t porta, portb, portc, portd;
- avr_uart_t uart0,uart1;
- avr_timer8_t timer0,timer2;
- avr_spi_t spi;
- avr_twi_t twi;
-} mcu = {
- .core = {
- .mmcu = "atmega644",
- DEFAULT_CORE(4),
-
- .init = init,
- .reset = reset,
- },
- AVR_EEPROM_DECLARE(EE_READY_vect),
- .extint = {
- AVR_EXTINT_DECLARE(0, 'D', PD2),
- AVR_EXTINT_DECLARE(1, 'D', PD3),
- AVR_EXTINT_DECLARE(2, 'B', PB3),
- },
- .porta = {
- .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
- .pcint = {
- .enable = AVR_IO_REGBIT(PCICR, PCIE0),
- .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
- .vector = PCINT0_vect,
- },
- .r_pcint = PCMSK0,
- },
- .portb = {
- .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
- .pcint = {
- .enable = AVR_IO_REGBIT(PCICR, PCIE1),
- .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
- .vector = PCINT1_vect,
- },
- .r_pcint = PCMSK1,
- },
- .portc = {
- .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
- .pcint = {
- .enable = AVR_IO_REGBIT(PCICR, PCIE2),
- .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
- .vector = PCINT2_vect,
- },
- .r_pcint = PCMSK2,
- },
- .portd = {
- .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
- .pcint = {
- .enable = AVR_IO_REGBIT(PCICR, PCIE3),
- .raised = AVR_IO_REGBIT(PCIFR, PCIF3),
- .vector = PCINT3_vect,
- },
- .r_pcint = PCMSK3,
- },
-
- .uart0 = {
- .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
- .name = '0',
- .r_udr = UDR0,
-
- .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
- .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
-
- .r_ucsra = UCSR0A,
- .r_ucsrb = UCSR0B,
- .r_ucsrc = UCSR0C,
- .r_ubrrl = UBRR0L,
- .r_ubrrh = UBRR0H,
- .rxc = {
- .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
- .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
- .vector = USART0_RX_vect,
- },
- .txc = {
- .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
- .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
- .vector = USART0_TX_vect,
- },
- .udrc = {
- .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
- .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
- .vector = USART0_UDRE_vect,
- },
- },
- .uart1 = {
- .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
- .name = '1',
- .r_udr = UDR1,
-
- .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
- .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
-
- .r_ucsra = UCSR1A,
- .r_ucsrb = UCSR1B,
- .r_ucsrc = UCSR1C,
- .r_ubrrl = UBRR1L,
- .r_ubrrh = UBRR1H,
- .rxc = {
- .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
- .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
- .vector = USART1_RX_vect,
- },
- .txc = {
- .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
- .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
- .vector = USART1_TX_vect,
- },
- .udrc = {
- .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
- .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
- .vector = USART1_UDRE_vect,
- },
- },
-
- .timer0 = {
- .name = '0',
- .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
- .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
- .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
-
- .r_ocra = OCR0A,
- .r_ocrb = OCR0B,
- .r_tcnt = TCNT0,
-
- .overflow = {
- .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
- .raised = AVR_IO_REGBIT(TIFR0, TOV0),
- .vector = TIMER0_OVF_vect,
- },
- .compa = {
- .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
- .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
- .vector = TIMER0_COMPA_vect,
- },
- .compb = {
- .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
- .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
- .vector = TIMER0_COMPB_vect,
- },
- },
- .timer2 = {
- .name = '2',
- .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
- .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
- .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
-
- .r_ocra = OCR2A,
- .r_ocrb = OCR2B,
- .r_tcnt = TCNT2,
-
- // asynchronous timer source bit.. if set, use 32khz frequency
- .as2 = AVR_IO_REGBIT(ASSR, AS2),
-
- .overflow = {
- .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
- .raised = AVR_IO_REGBIT(TIFR2, TOV2),
- .vector = TIMER2_OVF_vect,
- },
- .compa = {
- .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
- .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
- .vector = TIMER2_COMPA_vect,
- },
- .compb = {
- .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
- .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
- .vector = TIMER2_COMPB_vect,
- },
- },
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
- .twi = {
- .disabled = AVR_IO_REGBIT(PRR,PRTWI),
-
- .r_twcr = TWCR,
- .r_twsr = TWSR,
- .r_twbr = TWBR,
- .r_twdr = TWDR,
- .r_twar = TWAR,
- .r_twamr = TWAMR,
-
- .twen = AVR_IO_REGBIT(TWCR, TWEN),
- .twea = AVR_IO_REGBIT(TWCR, TWEA),
- .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
- .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
- .twwc = AVR_IO_REGBIT(TWCR, TWWC),
-
- .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
- .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
-
- .twi = {
- .enable = AVR_IO_REGBIT(TWCR, TWIE),
- .raised = AVR_IO_REGBIT(TWSR, TWINT),
- .vector = TWI_vect,
- },
- },
-
-};
+// instanciate the new core
+#include "sim_megax4.h"
static avr_t * make()
{
- return &mcu.core;
+ return &SIM_CORENAME.core;
}
avr_kind_t mega644 = {
@@ -268,27 +40,3 @@ avr_kind_t mega644 = {
.make = make
};
-static void init(struct avr_t * avr)
-{
- struct mcu_t * mcu = (struct mcu_t*)avr;
-
- printf("%s init\n", avr->mmcu);
-
- avr_eeprom_init(avr, &mcu->eeprom);
- avr_extint_init(avr, &mcu->extint);
- avr_ioport_init(avr, &mcu->porta);
- avr_ioport_init(avr, &mcu->portb);
- avr_ioport_init(avr, &mcu->portc);
- avr_ioport_init(avr, &mcu->portd);
- avr_uart_init(avr, &mcu->uart0);
- avr_uart_init(avr, &mcu->uart1);
- avr_timer8_init(avr, &mcu->timer0);
- avr_timer8_init(avr, &mcu->timer2);
- avr_spi_init(avr, &mcu->spi);
- avr_twi_init(avr, &mcu->twi);
-}
-
-static void reset(struct avr_t * avr)
-{
-// struct mcu_t * mcu = (struct mcu_t*)avr;
-}
diff --git a/simavr/cores/sim_megax4.c b/simavr/cores/sim_megax4.c
new file mode 100644
index 0000000..0dc259b
--- /dev/null
+++ b/simavr/cores/sim_megax4.c
@@ -0,0 +1,49 @@
+/*
+ sim_megax4.c
+
+ Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
+
+ This file is part of simavr.
+
+ simavr is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ simavr is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with simavr. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <stdio.h>
+#include "sim_avr.h"
+
+#include "sim_megax4.h"
+
+void mx4_init(struct avr_t * avr)
+{
+ struct mcu_t * mcu = (struct mcu_t*)avr;
+
+ printf("%s init\n", avr->mmcu);
+
+ avr_eeprom_init(avr, &mcu->eeprom);
+ avr_extint_init(avr, &mcu->extint);
+ avr_ioport_init(avr, &mcu->porta);
+ avr_ioport_init(avr, &mcu->portb);
+ avr_ioport_init(avr, &mcu->portc);
+ avr_ioport_init(avr, &mcu->portd);
+ avr_uart_init(avr, &mcu->uart0);
+ avr_uart_init(avr, &mcu->uart1);
+ avr_timer8_init(avr, &mcu->timer0);
+ avr_timer8_init(avr, &mcu->timer2);
+ avr_spi_init(avr, &mcu->spi);
+ avr_twi_init(avr, &mcu->twi);
+}
+
+void mx4_reset(struct avr_t * avr)
+{
+// struct mcu_t * mcu = (struct mcu_t*)avr;
+}
diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
new file mode 100644
index 0000000..328b364
--- /dev/null
+++ b/simavr/cores/sim_megax4.h
@@ -0,0 +1,271 @@
+/*
+ sim_megax4.h
+
+ Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
+
+ This file is part of simavr.
+
+ simavr is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ simavr is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with simavr. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SIM_MEGAX4_H__
+#define __SIM_MEGAX4_H__
+
+#include "sim_avr.h"
+#include "sim_core_declare.h"
+#include "avr_eeprom.h"
+#include "avr_extint.h"
+#include "avr_ioport.h"
+#include "avr_uart.h"
+#include "avr_timer8.h"
+#include "avr_spi.h"
+#include "avr_twi.h"
+
+void mx4_init(struct avr_t * avr);
+void mx4_reset(struct avr_t * avr);
+
+/*
+ * This is a template for all of the x4 devices, hopefuly
+ */
+struct mcu_t {
+ avr_t core;
+ avr_eeprom_t eeprom;
+ avr_extint_t extint;
+ avr_ioport_t porta, portb, portc, portd;
+ avr_uart_t uart0,uart1;
+ avr_timer8_t timer0,timer2;
+ avr_spi_t spi;
+ avr_twi_t twi;
+};
+
+#ifdef SIM_CORENAME
+
+#ifndef SIM_MMCU
+#error SIM_MMCU is not declared
+#endif
+
+struct mcu_t SIM_CORENAME = {
+ .core = {
+ .mmcu = SIM_MMCU,
+ DEFAULT_CORE(4),
+
+ .init = mx4_init,
+ .reset = mx4_reset,
+ },
+ AVR_EEPROM_DECLARE(EE_READY_vect),
+ .extint = {
+ AVR_EXTINT_DECLARE(0, 'D', PD2),
+ AVR_EXTINT_DECLARE(1, 'D', PD3),
+ AVR_EXTINT_DECLARE(2, 'B', PB3),
+ },
+ .porta = {
+ .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
+ .pcint = {
+ .enable = AVR_IO_REGBIT(PCICR, PCIE0),
+ .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
+ .vector = PCINT0_vect,
+ },
+ .r_pcint = PCMSK0,
+ },
+ .portb = {
+ .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
+ .pcint = {
+ .enable = AVR_IO_REGBIT(PCICR, PCIE1),
+ .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
+ .vector = PCINT1_vect,
+ },
+ .r_pcint = PCMSK1,
+ },
+ .portc = {
+ .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
+ .pcint = {
+ .enable = AVR_IO_REGBIT(PCICR, PCIE2),
+ .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
+ .vector = PCINT2_vect,
+ },
+ .r_pcint = PCMSK2,
+ },
+ .portd = {
+ .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
+ .pcint = {
+ .enable = AVR_IO_REGBIT(PCICR, PCIE3),
+ .raised = AVR_IO_REGBIT(PCIFR, PCIF3),
+ .vector = PCINT3_vect,
+ },
+ .r_pcint = PCMSK3,
+ },
+
+ .uart0 = {
+ .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
+ .name = '0',
+ .r_udr = UDR0,
+
+ .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
+ .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+
+ .r_ucsra = UCSR0A,
+ .r_ucsrb = UCSR0B,
+ .r_ucsrc = UCSR0C,
+ .r_ubrrl = UBRR0L,
+ .r_ubrrh = UBRR0H,
+ .rxc = {
+ .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
+ .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
+ .vector = USART0_RX_vect,
+ },
+ .txc = {
+ .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
+ .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
+ .vector = USART0_TX_vect,
+ },
+ .udrc = {
+ .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
+ .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
+ .vector = USART0_UDRE_vect,
+ },
+ },
+ .uart1 = {
+ .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
+ .name = '1',
+ .r_udr = UDR1,
+
+ .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
+ .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
+
+ .r_ucsra = UCSR1A,
+ .r_ucsrb = UCSR1B,
+ .r_ucsrc = UCSR1C,
+ .r_ubrrl = UBRR1L,
+ .r_ubrrh = UBRR1H,
+ .rxc = {
+ .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
+ .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
+ .vector = USART1_RX_vect,
+ },
+ .txc = {
+ .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
+ .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
+ .vector = USART1_TX_vect,
+ },
+ .udrc = {
+ .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
+ .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
+ .vector = USART1_UDRE_vect,
+ },
+ },
+
+ .timer0 = {
+ .name = '0',
+ .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
+ .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
+ .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
+
+ .r_ocra = OCR0A,
+ .r_ocrb = OCR0B,
+ .r_tcnt = TCNT0,
+
+ .overflow = {
+ .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
+ .raised = AVR_IO_REGBIT(TIFR0, TOV0),
+ .vector = TIMER0_OVF_vect,
+ },
+ .compa = {
+ .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
+ .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
+ .vector = TIMER0_COMPA_vect,
+ },
+ .compb = {
+ .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
+ .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
+ .vector = TIMER0_COMPB_vect,
+ },
+ },
+ .timer2 = {
+ .name = '2',
+ .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
+ .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
+ .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
+
+ .r_ocra = OCR2A,
+ .r_ocrb = OCR2B,
+ .r_tcnt = TCNT2,
+
+ // asynchronous timer source bit.. if set, use 32khz frequency
+ .as2 = AVR_IO_REGBIT(ASSR, AS2),
+
+ .overflow = {
+ .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
+ .raised = AVR_IO_REGBIT(TIFR2, TOV2),
+ .vector = TIMER2_OVF_vect,
+ },
+ .compa = {
+ .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
+ .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
+ .vector = TIMER2_COMPA_vect,
+ },
+ .compb = {
+ .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
+ .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
+ .vector = TIMER2_COMPB_vect,
+ },
+ },
+ .spi = {
+ .disabled = AVR_IO_REGBIT(PRR,PRSPI),
+
+ .r_spdr = SPDR,
+ .r_spcr = SPCR,
+ .r_spsr = SPSR,
+
+ .spe = AVR_IO_REGBIT(SPCR, SPE),
+ .mstr = AVR_IO_REGBIT(SPCR, MSTR),
+
+ .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
+ .spi = {
+ .enable = AVR_IO_REGBIT(SPCR, SPIE),
+ .raised = AVR_IO_REGBIT(SPSR, SPIF),
+ .vector = SPI_STC_vect,
+ },
+ },
+
+ .twi = {
+ .disabled = AVR_IO_REGBIT(PRR,PRTWI),
+
+ .r_twcr = TWCR,
+ .r_twsr = TWSR,
+ .r_twbr = TWBR,
+ .r_twdr = TWDR,
+ .r_twar = TWAR,
+ .r_twamr = TWAMR,
+
+ .twen = AVR_IO_REGBIT(TWCR, TWEN),
+ .twea = AVR_IO_REGBIT(TWCR, TWEA),
+ .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
+ .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
+ .twwc = AVR_IO_REGBIT(TWCR, TWWC),
+
+ .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
+ .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
+
+ .twi = {
+ .enable = AVR_IO_REGBIT(TWCR, TWIE),
+ .raised = AVR_IO_REGBIT(TWSR, TWINT),
+ .vector = TWI_vect,
+ },
+ },
+
+};
+
+#endif /* SIM_CORENAME */
+
+#endif /* __SIM_MEGAX4_H__ */
diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index 2e220b9..3124df9 100644
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -68,8 +68,8 @@ struct mcu_t SIM_CORENAME = {
},
AVR_EEPROM_DECLARE(EE_READY_vect),
.extint = {
- AVR_EXTINT_DECLARE(0, 'D', PD2),
- AVR_EXTINT_DECLARE(1, 'D', PD3),
+ AVR_EXTINT_DECLARE(0, 'D', 2),
+ AVR_EXTINT_DECLARE(1, 'D', 3),
},
.portb = {
.name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
diff --git a/simavr/sim/sim_avr.c b/simavr/sim/sim_avr.c
index 28c18a0..e0f9cb7 100644
--- a/simavr/sim/sim_avr.c
+++ b/simavr/sim/sim_avr.c
@@ -285,18 +285,14 @@ int avr_run(avr_t * avr)
extern avr_kind_t tiny13;
extern avr_kind_t tiny25,tiny45,tiny85;
-extern avr_kind_t mega48,mega88,mega168;
-extern avr_kind_t mega644;
+extern avr_kind_t mega48,mega88,mega168,mega328;
+extern avr_kind_t mega164,mega324,mega644;
avr_kind_t * avr_kind[] = {
&tiny13,
- &tiny25,
- &tiny45,
- &tiny85,
- &mega48,
- &mega88,
- &mega168,
- &mega644,
+ &tiny25, &tiny45, &tiny85,
+ &mega48, &mega88, &mega168, &mega328,
+ &mega164, &mega324, &mega644,
NULL
};