From: lleroy <lode.leroy@gmail.com>
Date: Thu, 16 Jan 2014 07:46:31 +0000 (+0100)
Subject: cores: Added atmega169p
X-Git-Tag: v1.2~11
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=36ae8cdeed3b9f40a5e9a7c388a4eae9b9a024f5;p=sx%2Fsimavr.git

cores: Added atmega169p
---

diff --git a/simavr/cores/sim_mega169.c b/simavr/cores/sim_mega169.c
new file mode 100644
index 0000000..93cb72b
--- /dev/null
+++ b/simavr/cores/sim_mega169.c
@@ -0,0 +1,380 @@
+/*
+	sim_mega169p.c
+ */
+
+#include "sim_avr.h"
+#include "sim_core_declare.h"
+#include "avr_eeprom.h"
+#include "avr_flash.h"
+#include "avr_watchdog.h"
+#include "avr_extint.h"
+#include "avr_ioport.h"
+#include "avr_uart.h"
+#include "avr_adc.h"
+#include "avr_timer.h"
+#include "avr_spi.h"
+#include "avr_twi.h"
+
+void m169p_init(struct avr_t * avr);
+void m169p_reset(struct avr_t * avr);
+
+#define _AVR_IO_H_
+#define __ASSEMBLER__
+#ifndef __AVR_ATmega169p__
+#define __AVR_ATmega169p__
+#endif
+#include "avr/iom169p.h"
+
+#if defined(MCUSR) && !defined(MCUCSR)
+#define MCUCSR MCUSR
+#endif
+
+const struct mcu_t {
+	avr_t          core;
+	avr_eeprom_t 	eeprom;
+	avr_flash_t 	selfprog;
+	avr_watchdog_t	watchdog;
+	avr_extint_t	extint;
+	avr_ioport_t	porta, portb, portc, portd, porte, portf, portg;
+	avr_uart_t		uart0;
+	avr_adc_t		adc;
+	avr_timer_t		timer0,timer1,timer2;
+	avr_spi_t		spi;
+	avr_twi_t		twi;
+ } mcu_mega169p = {
+	.core = {
+		.mmcu = "atmega169p",
+		DEFAULT_CORE(4),
+
+		.init = m169p_init,
+		.reset = m169p_reset,
+	},
+	AVR_EEPROM_DECLARE_NOEEPM(EE_READY_vect),
+	AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
+	AVR_WATCHDOG_DECLARE_128(WDTCR, _VECTOR(0)),
+	.extint = {
+		AVR_EXTINT_DECLARE(0, 'D', PD1),
+	},
+	.porta = {
+		.name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
+	},
+	.portb = {
+		.name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,  .r_pcint = PCMSK1,
+		.pcint = {
+			.enable = AVR_IO_REGBIT(EIMSK, PCIE1),
+			.raised = AVR_IO_REGBIT(EIFR, PCIF1),
+			.vector = PCINT1_vect,
+		},
+	},
+	.portc = {
+		.name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
+	},
+	.portd = {
+		.name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
+	},
+	.porte = {
+		.name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE, .r_pcint = PCMSK0,
+		.pcint = {
+			.enable = AVR_IO_REGBIT(EIMSK, PCIE0),
+			.raised = AVR_IO_REGBIT(EIFR, PCIF0),
+			.vector = PCINT0_vect,
+		},
+	},
+	.portf = {
+		.name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
+	},
+	.portg = {
+		.name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
+	},
+
+	.uart0 = {
+		.name = '0',
+		.r_udr = UDR0,
+
+		.txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
+		.rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+		.ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), 	// 1 bits
+
+		.r_ucsra = UCSR0A,
+		.r_ucsrb = UCSR0B,
+		.r_ucsrc = UCSR0C,
+		.r_ubrrl = UBRR0L,
+		.r_ubrrh = UBRR0H,
+		.rxc = {
+			.enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
+			.raised = AVR_IO_REGBIT(UCSR0A, RXC0),
+			.vector = USART0_RX_vect,
+		},
+		.txc = {
+			.enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
+			.raised = AVR_IO_REGBIT(UCSR0A, TXC0),
+			.vector = USART0_TX_vect,
+		},
+		.udrc = {
+			.enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
+			.raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
+			.vector = USART0_UDRE_vect,
+		},
+	},
+	.adc = {
+		.r_admux = ADMUX,
+		.mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
+					AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
+					AVR_IO_REGBIT(ADMUX, MUX4),
+        },
+		.ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
+		.ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V110},
+
+		.adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
+		.r_adcsra = ADCSRA,
+		.aden = AVR_IO_REGBIT(ADCSRA, ADEN),
+		.adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
+		.adate = AVR_IO_REGBIT(ADCSRA, ADATE),
+		.adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
+
+		.r_adch = ADCH,
+		.r_adcl = ADCL,
+
+		.r_adcsrb = ADCSRB,
+		.adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
+
+		.muxmode = {
+			[0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
+			[2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
+			[4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
+			[6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
+
+			[ 8] = AVR_ADC_DIFF(0, 0,  10), [ 9] = AVR_ADC_DIFF(1, 0,  10),
+			[10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
+			[12] = AVR_ADC_DIFF(2, 2,  10), [13] = AVR_ADC_DIFF(3, 2,  10),
+			[14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
+
+			[16] = AVR_ADC_DIFF(0, 1,   1), [17] = AVR_ADC_DIFF(1, 1,   1),
+			[18] = AVR_ADC_DIFF(2, 1,   1), [19] = AVR_ADC_DIFF(3, 1,   1),
+			[20] = AVR_ADC_DIFF(4, 1,   1), [21] = AVR_ADC_DIFF(5, 1,   1),
+			[22] = AVR_ADC_DIFF(6, 1,   1), [23] = AVR_ADC_DIFF(7, 1,   1),
+
+			[24] = AVR_ADC_DIFF(0, 2,   1), [25] = AVR_ADC_DIFF(1, 2,   1),
+			[26] = AVR_ADC_DIFF(2, 2,   1), [27] = AVR_ADC_DIFF(3, 2,   1),
+			[28] = AVR_ADC_DIFF(4, 2,   1), [29] = AVR_ADC_DIFF(5, 2,   1),
+
+			[30] = AVR_ADC_REF(1100),	// 1.1V
+			[31] = AVR_ADC_REF(0),		// GND
+
+			[32] = AVR_ADC_SINGLE( 8), [33] = AVR_ADC_SINGLE( 9),
+			[34] = AVR_ADC_SINGLE(10), [35] = AVR_ADC_SINGLE(11),
+			[36] = AVR_ADC_SINGLE(12), [37] = AVR_ADC_SINGLE(13),
+			[38] = AVR_ADC_SINGLE(14), [39] = AVR_ADC_SINGLE(15),
+
+			[40] = AVR_ADC_DIFF( 8,  8,  10), [41] = AVR_ADC_DIFF( 9,  8,  10),
+			[42] = AVR_ADC_DIFF( 8,  8, 200), [43] = AVR_ADC_DIFF( 9,  8, 200),
+
+			[44] = AVR_ADC_DIFF(10, 10,  10), [45] = AVR_ADC_DIFF(11, 10,  10),
+			[46] = AVR_ADC_DIFF(10, 10, 200), [47] = AVR_ADC_DIFF(11, 10, 200),
+
+			[48] = AVR_ADC_DIFF( 8,  9,   1), [49] = AVR_ADC_DIFF( 9,  9,   1),
+			[50] = AVR_ADC_DIFF(10,  9,   1), [51] = AVR_ADC_DIFF(11,  9,   1),
+			[52] = AVR_ADC_DIFF(12,  9,   1), [53] = AVR_ADC_DIFF(13,  9,   1),
+			[54] = AVR_ADC_DIFF(14,  9,   1), [55] = AVR_ADC_DIFF(15,  9,   1),
+
+			[56] = AVR_ADC_DIFF( 8, 10,   1), [57] = AVR_ADC_DIFF( 9, 10,   1),
+			[58] = AVR_ADC_DIFF(10, 10,   1), [59] = AVR_ADC_DIFF(11, 10,   1),
+			[60] = AVR_ADC_DIFF(12, 10,   1), [61] = AVR_ADC_DIFF(13, 10,   1),
+		},
+
+		.adc = {
+			.enable = AVR_IO_REGBIT(ADCSRA, ADIE),
+			.raised = AVR_IO_REGBIT(ADCSRA, ADIF),
+			.vector = ADC_vect,
+		},
+	},
+	.timer0 = {
+		.name = '0',
+		.wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01) },
+		.wgm_op = {
+			[0] = AVR_TIMER_WGM_NORMAL8(),
+			[2] = AVR_TIMER_WGM_CTC(),
+			[3] = AVR_TIMER_WGM_FASTPWM8(),
+			[7] = AVR_TIMER_WGM_OCPWM(),
+		},
+		.cs = { AVR_IO_REGBIT(TCCR0A, CS00), AVR_IO_REGBIT(TCCR0A, CS01), AVR_IO_REGBIT(TCCR0A, CS02) },
+		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
+
+		.r_tcnt = TCNT0,
+
+		.overflow = {
+			.enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
+			.raised = AVR_IO_REGBIT(TIFR0, TOV0),
+			.vector = TIMER0_OVF_vect,
+		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR0A,
+				.com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
+				.com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
+					.raised = AVR_IO_REGBIT(TIFR0, OCF0A),
+					.vector = TIMER0_COMP_vect,
+				},
+			},
+		},
+	},
+	.timer1 = {
+		.name = '1',
+		.disabled = AVR_IO_REGBIT(PRR,PRTIM1),
+		.wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
+					AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
+		.wgm_op = {
+			[0] = AVR_TIMER_WGM_NORMAL16(),
+			// TODO: 1 PWM phase correct 8bit
+			// 		 2 PWM phase correct 9bit
+			//       3 PWM phase correct 10bit
+			[4] = AVR_TIMER_WGM_CTC(),
+			[5] = AVR_TIMER_WGM_FASTPWM8(),
+			[6] = AVR_TIMER_WGM_FASTPWM9(),
+			[7] = AVR_TIMER_WGM_FASTPWM10(),
+			// TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
+			[12] = AVR_TIMER_WGM_ICCTC(),
+			[14] = AVR_TIMER_WGM_ICPWM(),
+			[15] = AVR_TIMER_WGM_OCPWM(),
+		},
+		.cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
+		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
+
+		.r_tcnt = TCNT1L,
+		.r_tcnth = TCNT1H,
+		.r_icr = ICR1L,
+		.r_icrh = ICR1H,
+
+		.ices = AVR_IO_REGBIT(TCCR1B, ICES1),
+		.icp = AVR_IO_REGBIT(PORTD, PD4),
+
+		.overflow = {
+			.enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
+			.raised = AVR_IO_REGBIT(TIFR1, TOV1),
+			.vector = TIMER1_OVF_vect,
+		},
+		.icr = {
+			.enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
+			.raised = AVR_IO_REGBIT(TIFR1, ICF1),
+			.vector = TIMER1_CAPT_vect,
+		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR1AL,
+				.r_ocrh = OCR1AH,	// 16 bits timers have two bytes of it
+				.com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
+				.com_pin = AVR_IO_REGBIT(PORTB, PB5),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
+					.raised = AVR_IO_REGBIT(TIFR1, OCF1A),
+					.vector = TIMER1_COMPA_vect,
+				},
+			},
+			[AVR_TIMER_COMPB] = {
+				.r_ocr = OCR1BL,
+				.r_ocrh = OCR1BH,
+				.com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
+				.com_pin = AVR_IO_REGBIT(PORTB, PB6),
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
+					.raised = AVR_IO_REGBIT(TIFR1, OCF1B),
+					.vector = TIMER1_COMPB_vect,
+				},
+			},
+		},
+
+	},
+	.timer2 = {
+		.name = '2',
+		.wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21) },
+		.wgm_op = {
+			[0] = AVR_TIMER_WGM_NORMAL8(),
+			// TODO 1 pwm phase correct 
+			[2] = AVR_TIMER_WGM_CTC(),
+			[3] = AVR_TIMER_WGM_FASTPWM8(),
+		},
+		.cs = { AVR_IO_REGBIT(TCCR2A, CS20), AVR_IO_REGBIT(TCCR2A, CS21), AVR_IO_REGBIT(TCCR2A, CS22) },
+		//.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
+		.cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ /* TODO external clock */ },
+        .as2 = AVR_IO_REGBIT(ASSR, AS2),
+		.r_tcnt = TCNT2,
+		.overflow = {
+			.enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
+			.raised = AVR_IO_REGBIT(TIFR2, TOV2),
+			.vector = TIMER2_OVF_vect,
+		},
+		.comp = {
+			[AVR_TIMER_COMPA] = {
+				.r_ocr = OCR2A,
+				.com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3), 
+				.com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
+				.interrupt = {
+					.enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
+					.raised = AVR_IO_REGBIT(TIFR2, OCF2A),
+					.vector = TIMER2_COMP_vect,
+				},
+			},
+		},
+	},
+	.spi = {
+		.disabled = AVR_IO_REGBIT(PRR,PRSPI),
+
+		.r_spdr = SPDR,
+		.r_spcr = SPCR,
+		.r_spsr = SPSR,
+
+		.spe = AVR_IO_REGBIT(SPCR, SPE),
+		.mstr = AVR_IO_REGBIT(SPCR, MSTR),
+
+		.spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
+		.spi = {
+			.enable = AVR_IO_REGBIT(SPCR, SPIE),
+			.raised = AVR_IO_REGBIT(SPSR, SPIF),
+			.vector = SPI_STC_vect,
+		},
+	},
+
+};
+
+static avr_t * make()
+{
+	return avr_core_allocate(&mcu_mega169p.core, sizeof(struct mcu_t));
+}
+
+avr_kind_t mega169p = {
+        .names = { "atmega169p" },
+        .make = make
+};
+
+void m169p_init(struct avr_t * avr)
+{
+	struct mcu_t * mcu = (struct mcu_t*)avr;
+
+	avr_eeprom_init(avr, &mcu->eeprom);
+	avr_flash_init(avr, &mcu->selfprog);
+	avr_extint_init(avr, &mcu->extint);
+	avr_watchdog_init(avr, &mcu->watchdog);
+	avr_ioport_init(avr, &mcu->porta);
+	avr_ioport_init(avr, &mcu->portb);
+	avr_ioport_init(avr, &mcu->portc);
+	avr_ioport_init(avr, &mcu->portd);
+	avr_ioport_init(avr, &mcu->porte);
+	avr_ioport_init(avr, &mcu->portf);
+	avr_ioport_init(avr, &mcu->portg);
+
+	avr_uart_init(avr, &mcu->uart0);
+	avr_adc_init(avr, &mcu->adc);
+	avr_timer_init(avr, &mcu->timer0);
+	avr_timer_init(avr, &mcu->timer1);
+	avr_timer_init(avr, &mcu->timer2);
+	avr_spi_init(avr, &mcu->spi);
+}
+
+void m169p_reset(struct avr_t * avr)
+{
+//	struct mcu_t * mcu = (struct mcu_t*)avr;
+}
+