From: bsekisser <squirmyworms@embarqmail.com>
Date: Sun, 13 Oct 2013 20:01:07 +0000 (-0400)
Subject: sim_core.c: fix implimentation of muls instruction
X-Git-Tag: v1.2~58^2
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=382900645b1f7244d1b29cc851314c3e194c84e3;p=sx%2Fsimavr.git

sim_core.c: fix implimentation of muls instruction

specification for muls insruction states 2 cycles, not one as implimented.

bug find credit goes to: Shay Green <gblargg@gmail.com>

	modified:   sim_core.c
---

diff --git a/simavr/sim/sim_core.c b/simavr/sim/sim_core.c
index 03d46ff..a30cefe 100644
--- a/simavr/sim/sim_core.c
+++ b/simavr/sim/sim_core.c
@@ -538,6 +538,7 @@ avr_flashaddr_t avr_run_one(avr_t * avr)
 									_avr_set_r(avr, 1, res >> 8);
 									avr->sreg[S_C] = (res >> 15) & 1;
 									avr->sreg[S_Z] = res == 0;
+									cycle++;
 									SREG();
 								}	break;
 								case 0x0300: {	// MUL Multiply 0000 0011 fddd frrr