From: Michel Pollet <github.com@pollet.net>
Date: Tue, 13 Oct 2020 13:29:33 +0000 (+0100)
Subject: Merge pull request #413 from bsekisser/sim_regbit_clear_check_valid_reg
X-Git-Tag: v1.7~8
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=753006e5a9fc3fbea5444088f9e962bcfb9d73e0;p=sx%2Fsimavr.git

Merge pull request #413 from bsekisser/sim_regbit_clear_check_valid_reg

Remove kludge "avr_uart_regbit_clear" from uart
---

753006e5a9fc3fbea5444088f9e962bcfb9d73e0
diff --cc simavr/sim/sim_regbit.h
index 76f4f5e,4b511e9..10ecc56
--- a/simavr/sim/sim_regbit.h
+++ b/simavr/sim/sim_regbit.h
@@@ -134,12 -116,11 +134,14 @@@ avr_regbit_get_raw
  	return (avr->data[a]) & (rb.mask << rb.bit);
  }
  
 -static inline uint8_t avr_regbit_clear(avr_t * avr, avr_regbit_t rb)
 +static inline uint8_t
 +avr_regbit_clear(
 +	avr_t * avr,
 +	avr_regbit_t rb)
  {
  	uint16_t a = rb.reg;
+ 	if (!a)
+ 		return 0;
  	uint8_t m = rb.mask << rb.bit;
  	avr_core_watch_write(avr, a, avr->data[a] & ~m);
  	return avr->data[a];