From: Michel Pollet <buserror@gmail.com>
Date: Wed, 14 Apr 2010 17:14:27 +0000 (+0100)
Subject: cores: Add (some) of the ADC mux data
X-Git-Tag: v1.0a3~7
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=8380de2b8f06cfefba8b5d4efd7def3a0f7e9231;p=sx%2Fsimavr.git

cores: Add (some) of the ADC mux data

Add ADC Mux data to the x8 and x4 cores. The others still needs
to be done. Also filled the reference voltages.

Signed-off-by: Michel Pollet <buserror@gmail.com>
---

diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index 6fd27ed..2f59a27 100644
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -178,6 +178,8 @@ struct mcu_t SIM_CORENAME = {
 					AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
 					AVR_IO_REGBIT(ADMUX, MUX4),},
 		.ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
+		.ref_values = { [1] = ADC_VREF_AVCC, [2] = ADC_VREF_V110, [3] = ADC_VREF_V256 },
+
 		.adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
 		.r_adcsra = ADCSRA,
 		.aden = AVR_IO_REGBIT(ADCSRA, ADEN),
@@ -191,6 +193,30 @@ struct mcu_t SIM_CORENAME = {
 		.r_adcsrb = ADCSRB,
 		.adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
 
+		.muxmode = {
+			[0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
+			[2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
+			[4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
+			[6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
+
+			[ 8] = AVR_ADC_DIFF(0, 0,  10), [ 9] = AVR_ADC_DIFF(1, 0,  10),
+			[10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
+			[12] = AVR_ADC_DIFF(2, 2,  10), [13] = AVR_ADC_DIFF(3, 2,  10),
+			[14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
+
+			[16] = AVR_ADC_DIFF(0, 1,   1), [17] = AVR_ADC_DIFF(1, 1,   1),
+			[18] = AVR_ADC_DIFF(2, 1,   1), [19] = AVR_ADC_DIFF(3, 1,   1),
+			[20] = AVR_ADC_DIFF(4, 1,   1), [21] = AVR_ADC_DIFF(5, 1,   1),
+			[22] = AVR_ADC_DIFF(6, 1,   1), [23] = AVR_ADC_DIFF(7, 1,   1),
+
+			[24] = AVR_ADC_DIFF(0, 2,   1), [25] = AVR_ADC_DIFF(1, 2,   1),
+			[26] = AVR_ADC_DIFF(2, 2,   1), [27] = AVR_ADC_DIFF(3, 2,   1),
+			[28] = AVR_ADC_DIFF(4, 2,   1), [29] = AVR_ADC_DIFF(5, 2,   1),
+
+			[30] = AVR_ADC_REF(1100),	// 1.1V
+			[31] = AVR_ADC_REF(0),		// GND
+		},
+
 		.adc = {
 			.enable = AVR_IO_REGBIT(ADCSRA, ADIE),
 			.raised = AVR_IO_REGBIT(ADCSRA, ADIF),
diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index 5575d77..4ffe209 100644
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -141,6 +141,8 @@ struct mcu_t SIM_CORENAME = {
 		.mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
 					AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
 		.ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
+		.ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V110, },
+
 		.adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
 		.r_adcsra = ADCSRA,
 		.aden = AVR_IO_REGBIT(ADCSRA, ADEN),
@@ -154,6 +156,14 @@ struct mcu_t SIM_CORENAME = {
 		.r_adcsrb = ADCSRB,
 		.adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
 
+		.muxmode = {
+			[0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
+			[2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
+			[4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
+			[6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_TEMP(),
+			[14] = AVR_ADC_REF(1100),	// 1.1V
+			[15] = AVR_ADC_REF(0),		// GND
+		},
 		.adc = {
 			.enable = AVR_IO_REGBIT(ADCSRA, ADIE),
 			.raised = AVR_IO_REGBIT(ADCSRA, ADIF),