From: Michel Pollet <buserror@gmail.com>
Date: Tue, 15 Mar 2011 13:35:51 +0000 (+0000)
Subject: cores: Added UART bit rate flags
X-Git-Tag: v1.0a8~9
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=9e52a7ecd4a00a02debd75184ff9daa8d170ac39;p=sx%2Fsimavr.git

cores: Added UART bit rate flags

Updated the cores that have UART(s) with extra flags.

Signed-off-by: Michel Pollet <buserror@gmail.com>
---

diff --git a/simavr/cores/sim_mega128.c b/simavr/cores/sim_mega128.c
index 6d4e1d8..460a66b 100644
--- a/simavr/cores/sim_mega128.c
+++ b/simavr/cores/sim_mega128.c
@@ -107,6 +107,8 @@ struct mcu_t {
 
 		.txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
 		.rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+		.ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), 	// 1 bits
 
 		.r_ucsra = UCSR0A,
 		.r_ucsrb = UCSR0B,
@@ -136,6 +138,8 @@ struct mcu_t {
 
 		.txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
 		.rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
+		.ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), 	// 1 bits
 
 		.r_ucsra = UCSR1A,
 		.r_ucsrb = UCSR1B,
diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index b2a892d..72599e3 100644
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -121,6 +121,8 @@ struct mcu_t SIM_CORENAME = {
 
 		.txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
 		.rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+		.ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), 	// 1 bits
 
 		.r_ucsra = UCSR0A,
 		.r_ucsrb = UCSR0B,
@@ -150,6 +152,8 @@ struct mcu_t SIM_CORENAME = {
 
 		.txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
 		.rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
+		.ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), 	// 1 bits
 
 		.r_ucsra = UCSR1A,
 		.r_ucsrb = UCSR1B,
diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index 280249f..c78874c 100644
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -114,6 +114,9 @@ struct mcu_t SIM_CORENAME = {
 
 		.txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
 		.rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
+		.usbs = AVR_IO_REGBIT(UCSR0C, USBS0),
+		.ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), 	// 1 bits
 
 		.r_ucsra = UCSR0A,
 		.r_ucsrb = UCSR0B,
diff --git a/simavr/cores/sim_tiny2313.c b/simavr/cores/sim_tiny2313.c
index d9136f3..faeffd1 100644
--- a/simavr/cores/sim_tiny2313.c
+++ b/simavr/cores/sim_tiny2313.c
@@ -83,6 +83,8 @@ static struct mcu_t {
 
 		.txen = AVR_IO_REGBIT(UCSRB, TXEN),
 		.rxen = AVR_IO_REGBIT(UCSRB, RXEN),
+		.ucsz = AVR_IO_REGBITS(UCSRC, UCSZ0, 0x3), // 2 bits
+		.ucsz2 = AVR_IO_REGBIT(UCSRB, UCSZ2), 	// 1 bits
 
 		.r_ucsra = UCSRA,
 		.r_ucsrb = UCSRB,