From: Michel Pollet <buserror@gmail.com>
Date: Thu, 15 Mar 2012 14:14:29 +0000 (+0000)
Subject: interrupts: Delivery fix
X-Git-Tag: v1.0b1~23
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=a384d39e32edfa5a7df6356d3421d8cd8663f299;p=sx%2Fsimavr.git

interrupts: Delivery fix

Polled interrupts as for the UART were borken. Now fixed.

Signed-off-by: Michel Pollet <buserror@gmail.com>
---

diff --git a/simavr/sim/sim_interrupts.c b/simavr/sim/sim_interrupts.c
index 3e094e5..9334b03 100644
--- a/simavr/sim/sim_interrupts.c
+++ b/simavr/sim/sim_interrupts.c
@@ -103,18 +103,18 @@ avr_raise_interrupt(
 	if (vector->raised.reg)
 		avr_regbit_set(avr, vector->raised);
 
-	// Mark the interrupt as pending
-	vector->pending = 1;
-
-	avr_int_table_p table = &avr->interrupts;
-
-	table->pending[table->pending_w++] = vector;
-	table->pending_w = INT_FIFO_MOD(table->pending_w);
-
 	avr_raise_irq(&vector->irq, 1);
 
 	// If the interrupt is enabled, attempt to wake the core
 	if (avr_regbit_get(avr, vector->enable)) {
+		// Mark the interrupt as pending
+		vector->pending = 1;
+
+		avr_int_table_p table = &avr->interrupts;
+
+		table->pending[table->pending_w++] = vector;
+		table->pending_w = INT_FIFO_MOD(table->pending_w);
+
 		if (!table->pending_wait)
 			table->pending_wait = 1;		// latency on interrupts ??
 		if (avr->state != cpu_Running) {