From: bsekisser <squirmyworms@embarqmail.com>
Date: Sat, 22 Mar 2014 12:13:06 +0000 (-0400)
Subject: sim_core: fix rcall instruction cycles...
X-Git-Tag: v1.2~6^2
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=ae52fb327a9b4a792f45760f407b6c7e69b3cf1d;p=sx%2Fsimavr.git

sim_core: fix rcall instruction cycles...

Based on the instrtiming.elf code and checking the Avr Instruction
 Manual, RCALL was found to be producing incorrect cycle counts.

Atmega; 3, 16-bit pc; 4, 22-bit pc.

Fixed accordingly.

	modified:   sim/sim_core.c
---

diff --git a/simavr/sim/sim_core.c b/simavr/sim/sim_core.c
index 6fb150e..781ee84 100644
--- a/simavr/sim/sim_core.c
+++ b/simavr/sim/sim_core.c
@@ -1360,7 +1360,7 @@ avr_flashaddr_t avr_run_one(avr_t * avr)
 		case 0xd000: {	// RCALL -- 1101 kkkk kkkk kkkk
 			get_o_12(opcode);
 			STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
-			cycle += _avr_push_addr(avr, new_pc) - 1;
+			cycle += _avr_push_addr(avr, new_pc);
 			new_pc = new_pc + (o << 1);
 			// 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
 			if (o != 0) {