From: Jochen Kiemes <jochen@kiemes.de>
Date: Mon, 11 Jan 2021 16:32:27 +0000 (+0100)
Subject: fix foc and interrupt clear for timer
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=afdff9e92424c1336ce7297134ff084ce378ce35;p=sx%2Fsimavr.git

fix foc and interrupt clear for timer
---

diff --git a/simavr/cores/sim_mega2560.h b/simavr/cores/sim_mega2560.h
index 7e8974c..56a3450 100644
--- a/simavr/cores/sim_mega2560.h
+++ b/simavr/cores/sim_mega2560.h
@@ -316,6 +316,7 @@ const struct mcu_t {
 					.r_ocrh = OCR1AH,	// 16 bits timers have two bytes of it
 					.com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
 					.com_pin = AVR_IO_REGBIT(PORTB, PB5),
+					.foc = AVR_IO_REGBIT(TCCR1C, FOC1A),
 					.interrupt = {
 						.enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
 						.raised = AVR_IO_REGBIT(TIFR1, OCF1A),
@@ -327,6 +328,7 @@ const struct mcu_t {
 					.r_ocrh = OCR1BH,
 					.com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
 					.com_pin = AVR_IO_REGBIT(PORTB, PB6),
+					.foc = AVR_IO_REGBIT(TCCR1C, FOC1B),
 					.interrupt = {
 						.enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
 						.raised = AVR_IO_REGBIT(TIFR1, OCF1B),
@@ -338,6 +340,7 @@ const struct mcu_t {
 					.r_ocrh = OCR1CH,
 					.com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
 					.com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer0A
+					.foc = AVR_IO_REGBIT(TCCR1C, FOC1C),
 					.interrupt = {
 						.enable = AVR_IO_REGBIT(TIMSK1, OCIE1C),
 						.raised = AVR_IO_REGBIT(TIFR1, OCF1C),
@@ -437,6 +440,7 @@ const struct mcu_t {
 				.r_ocrh = OCR3AH,	// 16 bits timers have two bytes of it
 				.com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTE, PE3),
+				.foc = AVR_IO_REGBIT(TCCR3C, FOC3A),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK3, OCIE3A),
 					.raised = AVR_IO_REGBIT(TIFR3, OCF3A),
@@ -448,6 +452,7 @@ const struct mcu_t {
 				.r_ocrh = OCR3BH,
 				.com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTE, PE4),
+				.foc = AVR_IO_REGBIT(TCCR3C, FOC3B),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK3, OCIE3B),
 					.raised = AVR_IO_REGBIT(TIFR3, OCF3B),
@@ -459,6 +464,7 @@ const struct mcu_t {
 				.r_ocrh = OCR3CH,
 				.com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTE, PE5),
+				.foc = AVR_IO_REGBIT(TCCR3C, FOC3C),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK3, OCIE3C),
 					.raised = AVR_IO_REGBIT(TIFR3, OCF3C),
@@ -519,6 +525,7 @@ const struct mcu_t {
 				.r_ocrh = OCR4AH,	// 16 bits timers have two bytes of it
 				.com = AVR_IO_REGBITS(TCCR4A, COM4A0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTH, PH3),
+				.foc = AVR_IO_REGBIT(TCCR4C, FOC4A),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK4, OCIE4A),
 					.raised = AVR_IO_REGBIT(TIFR4, OCF4A),
@@ -530,6 +537,7 @@ const struct mcu_t {
 				.r_ocrh = OCR4BH,
 				.com = AVR_IO_REGBITS(TCCR4A, COM4B0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTH, PH4),
+				.foc = AVR_IO_REGBIT(TCCR4C, FOC4B),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK4, OCIE4B),
 					.raised = AVR_IO_REGBIT(TIFR4, OCF4B),
@@ -541,6 +549,7 @@ const struct mcu_t {
 				.r_ocrh = OCR4CH,
 				.com = AVR_IO_REGBITS(TCCR4A, COM4C0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTH, PH5),
+				.foc = AVR_IO_REGBIT(TCCR4C, FOC4C),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK4, OCIE4C),
 					.raised = AVR_IO_REGBIT(TIFR4, OCF4C),
@@ -597,6 +606,7 @@ const struct mcu_t {
 				.r_ocrh = OCR5AH,	// 16 bits timers have two bytes of it
 				.com = AVR_IO_REGBITS(TCCR5A, COM5A0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTL, PL3),
+				.foc = AVR_IO_REGBIT(TCCR5C, FOC5A),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK5, OCIE5A),
 					.raised = AVR_IO_REGBIT(TIFR5, OCF5A),
@@ -608,6 +618,7 @@ const struct mcu_t {
 				.r_ocrh = OCR5BH,
 				.com = AVR_IO_REGBITS(TCCR5A, COM5B0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTL, PL4),
+				.foc = AVR_IO_REGBIT(TCCR5C, FOC5B),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK5, OCIE5B),
 					.raised = AVR_IO_REGBIT(TIFR5, OCF5B),
@@ -619,6 +630,7 @@ const struct mcu_t {
 				.r_ocrh = OCR5CH,
 				.com = AVR_IO_REGBITS(TCCR5A, COM5C0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTL, PL5),
+				.foc = AVR_IO_REGBIT(TCCR5C, FOC5C),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK5, OCIE5C),
 					.raised = AVR_IO_REGBIT(TIFR5, OCF5C),
diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index 3bd65cb..ecb5971 100644
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -279,6 +279,7 @@ const struct mcu_t SIM_CORENAME = {
 				.r_ocrh = OCR1AH,	// 16 bits timers have two bytes of it
 				.com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTB, 1),
+                .foc = AVR_IO_REGBIT(TCCR1C, FOC1A),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
 					.raised = AVR_IO_REGBIT(TIFR1, OCF1A),
@@ -290,6 +291,7 @@ const struct mcu_t SIM_CORENAME = {
 				.r_ocrh = OCR1BH,
 				.com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
 				.com_pin = AVR_IO_REGBIT(PORTB, 2),
+                .foc = AVR_IO_REGBIT(TCCR1C, FOC1B),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
 					.raised = AVR_IO_REGBIT(TIFR1, OCF1B),
diff --git a/simavr/sim/avr_timer.c b/simavr/sim/avr_timer.c
index b9823a1..66a47ae 100644
--- a/simavr/sim/avr_timer.c
+++ b/simavr/sim/avr_timer.c
@@ -754,11 +754,14 @@ avr_timer_write_pending(
 	// avr_core_watch_write(avr, addr, v); // This raises flags instead of clearing it.
 
 	// clear any interrupts & flags
-	avr_clear_interrupt_if(avr, &p->overflow, ov);
-	avr_clear_interrupt_if(avr, &p->icr, ic);
+	if (avr_regbit_from_value(avr, p->overflow, v))
+		avr_clear_interrupt_if(avr, &p->overflow, ov);
+	if (avr_regbit_from_value(avr, p->icr, v))
+		avr_clear_interrupt_if(avr, &p->icr, ic);
 
 	for (int compi = 0; compi < AVR_TIMER_COMP_COUNT; compi++)
-		avr_clear_interrupt_if(avr, &p->comp[compi].interrupt, cp[compi]);
+		if (avr_regbit_from_value(avr, p->comp[compi].interrupt.raised, v))
+			avr_clear_interrupt_if(avr, &p->comp[compi].interrupt, cp[compi]);
 }
 
 static void