From: Thomas Martens <thomas@defaultschuldiger.de>
Date: Sat, 12 Oct 2019 20:04:20 +0000 (+0200)
Subject: added OC0A/OC0B support for attiny13
X-Git-Tag: v1.7~35^2
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=bf47f08521ca2b9533d3ce84ca05df789a79e0a4;p=sx%2Fsimavr.git

added OC0A/OC0B support for attiny13

.com and .com_pin settings for timer0 in section .comp were missed
---

diff --git a/simavr/cores/sim_tiny13.c b/simavr/cores/sim_tiny13.c
index a741ef4..06017ed 100644
--- a/simavr/cores/sim_tiny13.c
+++ b/simavr/cores/sim_tiny13.c
@@ -106,6 +106,8 @@ static const struct mcu_t {
 		.comp = {
 			[AVR_TIMER_COMPA] = {
 				.r_ocr = OCR0A,
+				.com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
+				.com_pin = AVR_IO_REGBIT(PORTB, 0),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
 					.raised = AVR_IO_REGBIT(TIFR0, OCF0A),
@@ -114,6 +116,8 @@ static const struct mcu_t {
 			},
 			[AVR_TIMER_COMPB] = {
 				.r_ocr = OCR0B,
+				.com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
+				.com_pin = AVR_IO_REGBIT(PORTB, 1),
 				.interrupt = {
 					.enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
 					.raised = AVR_IO_REGBIT(TIFR0, OCF0B),