From: Doug Goldstein <cardoe@cardoe.com>
Date: Sun, 27 Apr 2014 19:32:33 +0000 (-0500)
Subject: cores: Fix PCINT8 for ATmega128RFA1 and ATmega128RFR2
X-Git-Tag: v1.2~1^2
X-Git-Url: https://git.htl-mechatronik.at/public/?a=commitdiff_plain;h=bffb2e8ccbd919d058ed408ba67fbe441c17a70e;p=sx%2Fsimavr.git

cores: Fix PCINT8 for ATmega128RFA1 and ATmega128RFR2

PCINT8 was previously not setup. Per the spec sheet it is on Port E pin
0.
---

diff --git a/simavr/cores/sim_mega128rfa1.c b/simavr/cores/sim_mega128rfa1.c
index 6904689..3a14079 100644
--- a/simavr/cores/sim_mega128rfa1.c
+++ b/simavr/cores/sim_mega128rfa1.c
@@ -93,6 +93,12 @@ const struct mcu_t {
 	},
 	.porte = {
 		.name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
+		.pcint = {
+			.enable = AVR_IO_REGBIT(PCICR, PCIE1),
+			.raised = AVR_IO_REGBIT(PCIFR, PCIF1),
+			.vector = PCINT1_vect,
+		},
+		.r_pcint = PCMSK1,
 	},
 	.portf = {
 		.name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
diff --git a/simavr/cores/sim_mega128rfr2.c b/simavr/cores/sim_mega128rfr2.c
index 63d5832..d4c8183 100644
--- a/simavr/cores/sim_mega128rfr2.c
+++ b/simavr/cores/sim_mega128rfr2.c
@@ -93,6 +93,12 @@ const struct mcu_t {
 	},
 	.porte = {
 		.name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
+		.pcint = {
+			.enable = AVR_IO_REGBIT(PCICR, PCIE1),
+			.raised = AVR_IO_REGBIT(PCIFR, PCIF1),
+			.vector = PCINT1_vect,
+		},
+		.r_pcint = PCMSK1,
 	},
 	.portf = {
 		.name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,