cores: AVR_IOPORT_DECLARE
convert port sructure declarations to macro AVR_IOPORT_DECLARE.
modified: simavr/cores/sim_90usb162.c
modified: simavr/cores/sim_mega128.c
modified: simavr/cores/sim_mega1280.c
modified: simavr/cores/sim_mega1281.c
modified: simavr/cores/sim_mega128rfa1.c
modified: simavr/cores/sim_mega128rfr2.c
modified: simavr/cores/sim_mega169.c
modified: simavr/cores/sim_mega2560.c
modified: simavr/cores/sim_megax.h
modified: simavr/cores/sim_tiny2313.c
modified: simavr/sim/avr_ioport.h
tests: Fix makefile
Was using ${OBJ} before it was declared.
Signed-off-by: Michel Pollet <buserror@gmail.com>
build: fix build of libsimavr.so
Was being linked with itself. Newer gcc are not amused.
Signed-off-by: Michel Pollet <buserror@gmail.com>
build: re-accelerated the build
Simavr used to build pretty quick, and it's been crawling for a while
now, turns out some of the enhancements we added to the SIMAVR path
detection were being evaluated a LOT.
So went to the makefile and made sure most of the static variables are
evaluated once only.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #94 from hedrok/master
Timer simulation fixes and improvements
Merge pull request #92 from cyrozap/master
Fix the issue where Intel HEX files with hex strings longer than 32 bytes would be truncated
Merge pull request #83 from bsekisser/master-core-run-many-limited
Changes to allow for free run in core between cycle timers
Merge pull request #82 from dougszumski/i2c_test_extension
examples: Extends i2ctest to include a second TWI driver
Enhance emulation of PWM mode
- Clear/set output pin on TOP when OCRnX is in clear/set mode,
previously it was changed only on TCNT=OCRnX
- Call PWM irq for OCRnB even when TOP is OCRnA
Fixes in avr_timer_reconfigure after refactoring
Several fixes after
fcce7868a2fe2ef028b7f6c1741a12380b82a9cc:
- Remove zeroing of mode in which erased mode
seleced in avr_timer_write
- Fix wrong brackets in ?: in avr_timer_wgm_pwm mode
sim_hex: Only decrement maxlen in read_hex_string when a byte is added to the array
Without this fix, the output to the buffer would be limited to maxlen/2 bytes
instead of maxlen. It is obvious from the implementation that the latter
behavior is the expected one, so the function has been altered to reflect that.
Merge pull request #88 from anthony-morel/master
fifo: prevent potential misuse of _get_write_size()
fifo: prevent potential misuse of _get_write_size()
Using the number obtained from _get_write_size() and writing that many
items to the fifo yields to _isempty() becoming true and not to
_isfull() becoming true.
I got caught assuming the latter.
To avoid thinking about edge cases and prevent potential misuse of
_get_write_size(), I suggest that it returns one unit less, thus, a
number between 0 and (fifo_size-1). E.g., if there is only one place
left in the fifo, i.e., _isfull() is true, it then returns 0, preventing
us to fill that place and get into a wrap overflow situation.
(Michel: Thanks for the great architecture you laid out and the great
code.)
Changes to allow for free run in core between cycle timers
with per interval limiting.
Average cycle times drop by about upwards of 50-60+ cycles per emulated cycle,
dependant on usage.
sim_avr.h: struct avr_t changed.
added members run_cycle_count and run_cycle_limit.
run_cycle_count is number of cycles till next cycle timer.
run_cycle_limit is maximum number of cycles to run per interval.
sim_core.c: avr_run_one
* run_one_again label added at top.
* clause added at end which loops to run_one_again given that the core
is still in a cpu_Running state, run_cycle_count is greater than
cycles, and no interrups are pending.
sim_cycle_timers.c:
* static avr_cycle_timer_return_sleep_run_cycles_limited() added.
run_cycle_count is bounded to run_cycle_limit.
returns sleep count unbounded, preserving original behavior.
* static avr_cycle_timer_reset_sleep_run_cycles_limited() added.
sets new run_cycle_count based on present list of cycle timers.
* avr_cycle_timer_reset() changed.
run_cycle_count and run_cycle_limit is set to default values.
* avr_cycle_timer_register() changed.
* avr_cycle_timer_cancel() changed.
* avr_cycle_timer_process() changed.
call the relevant function to set/maintain run_cycle_count.
modified: simavr/sim/sim_avr.c
modified: simavr/sim/sim_avr.h
modified: simavr/sim/sim_cycle_timers.c
examples: Extends i2ctest to include a second TWI driver
Adds a commonly used alternative to the Atmel TWI driver. This
particular driver is choosen because it covers a non-interrupt
driven approach to using the TWI module.
Merge pull request #81 from dougszumski/ssd1306_demo
examples: Removed unused code in ssd1306 demo
Merge pull request #80 from dougszumski/avr_twi_bugfix
twi: Clear TWSTO bit after STOP condition transmitted
examples: Removed unused code in ssd1306 demo
twi: Clear TWSTO bit after STOP condition transmitted
> This change fixes a problem where a TWI driver polling the
TWSTO bit would run on the real device but not simavr.
> More detail in for example p188 of the ATMega32A datasheet
(rev 815D-AVR-10/2013).
Merge pull request #78 from dougszumski/i2c_eeprom_bugfix
parts: Bug fix for i2c_eeprom part
cores; 128rfr2, tiny84 and megax8, temp fix for bad arv-libc headers
Temporary, to make the build work. Seems the latest avr-libc in debian
is rather mangled.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Makefile: fix for OSX bash variable substitution
This was generating a bad config file
Signed-off-by: Michel Pollet <buserror@gmail.com>
parts: Bug fix for i2c_eeprom part
Fixes:
> Part address and mask weren't set in i2c_eeprom_init. The
virtual part responded to all addresses.
> Mask required inverting to function as per the description in
i2c_eeprom.h
Merge pull request #57 from bsekisser/avr-timer-as2-cs-mode
avr_timer: refactor avr_timer_write and avr_timer_reconfigure
Merge pull request #77 from dougszumski/ssd1306_demo
New part & example for a SSD1306 OLED driver
examples: Added SSD1306 example board
atmega32_ssd1306.c Example avr firmware
ssd1306.* SSD1306 avr driver
images.* simavr logo used in example firmware
ssd1306demo.c simavr demo for ssd1306 part
parts: Added SSD1306 OLED driver virtual part
avr_timer: refactor avr_timer_write and avr_timer_reconfigure
avr_timer_reconfigure: calculations moved back in call chain to
avr_timer_write.
avr_timer_configure: use data processed in avr_timer_write.
avr_timer_init: changed to fully trap writes going to as2,
clock select bits and waveform generation mode bits.
modified: ../../simavr/sim/avr_timer.c
modified: ../../simavr/sim/avr_timer.h
avr_timer: remove as2 timer check.
modified: avr_timer.c
Merge pull request #70 from cardoe/flash-fix
flash: Add support for TEMPPAGE writing.
Update README.md
Lots of cores were missing in the readme
make: Link libelf in libsimavr.so.1 target
The build (sometimes) fails if libsimavr.so.1 is not linked with
libelf (see https://bugs.archlinux.org/task/40309).
Merge pull request #73 from cardoe/rfa1-rfr2-pcint8
cores: Fix PCINT8 for ATmega128RFA1 and ATmega128RFR2
cores: Fix PCINT8 for ATmega128RFA1 and ATmega128RFR2
PCINT8 was previously not setup. Per the spec sheet it is on Port E pin
0.
flash: Add support for TEMPPAGE writing.
The proper way to write to flash on the AVR is to write
to the temp page and then write that temp page to flash.
This allows cancellation with the RWWSRE bit for clearing
out the temp page without writing it to flash.
This fixed a bug where the RWWSRE bit was being set in a
command, but the flash driver was improperly writing whatever
was in r0/r1 to the first address in the page, overwriting
what was already there. In reality, the code running on the
core was trying to just flush the temp page or unlock the read
while write section.
Merge pull request #72 from cardoe/rfr2
Support for ATmega128RFR2
cores: RFA1/RFR2 don't have Port A and Port C
The ATmega128RFA1 and ATmega128RFR2 don't actually have Port A and Port
C as IO pins.
cores: Add initial support for ATmega128RFR2
Add initial support for the ATmega128RFR2 which according to Atmel is a
drop in replacement for the ATmega128RFA1 however in real world testing
I have found this to not be entirely true. All of the changes (new
features) added to the R2 are not exposed with current simavr
peripherals so this file is identical to the A1 in simavr.
Clean up outdated comment
This comment is no longer true for any of the listed platforms so its
best to adjust the wording to what might be relevant to users
cores: Fix ADCH and ADCL to use defines for RFA1
No current release provides these defines however they are fixed in
avr-libc trunk and as such we should use them if they are available.
Merge pull request #71 from bsekisser/master-core-fixes-reductions
sim_core: fixes and reductions
sim_core: fixes and reductions
correct a few goofed up opcode descriptions.
get_d5 and get_r5: remove trailing slash on last macro line
add get_vd5: get_vd5 pulls in from get_d5 plus loads from register...
removes one definate instance of a possible double load, also
potentially removes double loads during tracing.
get_d5_b3 changed to get_vd5_b3: as all instances use the value of
reg d. get_vd5_b3 pulls in from get_vd5. reduces one definate
instance for potential of double loads and possibly reducing
the potential during tracing.
add get_vd5_b3_mask: two instances use b3 as a mask, get_vd5_b3_mask
pulls in from get_vd5_b3.
add get vh4_k8: get_vh4_k8 pulls in from get_h4_k8, removes the extra
line to pull in from the register... removes possible double
load during tracing.
get_p2_k6 changed to get_vp2_k6: register load was moved into the macro
as both instances need the value loaded from the register pair.
add get_io5 and get_io5_b3mask: get io5_b3 and get_io5_b3mask pulls in
from get_io5... most instances using get_io5_b3 take bit
number and use it as a mask, get_io5_b3mask does that by default.
get_o12: rcall and rjmp both left shift the value back before using
the offset... the macro just calls for one less bit to be
shifted... during trace we then make the extra shift as needed.
modified: sim/sim_core.c
Merge pull request #67 from bsekisser/master-core-refactor-flags
sim_core: flag equations refactored.
Merge pull request #69 from bsekisser/master-core-ldi-labeling-misc
sim_core: add ldi, trace and labeling corrections.
sim_core: flag equations refactored.
Most flag equations have been refactored into flag group function
blocks... The core passes all provided tests in the tests folder
and now most especially is able to pass the instruction test code.
At the same time, the overall average cycles per instruction has
ticked down.
modified: sim/sim_core.c
sim_core: add ldi, labeling corrections.
in moving the majority of instructions to follow use of register
macros, ldi was missed.
get_h4_k16() was incorrectly labeled where get_h4_k8() was intended
as k is an 8 bit quantity not 16.
get_o_12() was changed to get_o12() following the convention set
forth with the other macros.
several trace statements were missed during the conversion and fixed.
ORI was incorrecly labeled as ANDI in the description and corrected.
modified: sim/sim_core.c
Merge pull request #68 from bsekisser/master-core-fix-rcall-cycles
sim_core: fix rcall instruction cycles...
sim_core: fix rcall instruction cycles...
Based on the instrtiming.elf code and checking the Avr Instruction
Manual, RCALL was found to be producing incorrect cycle counts.
Atmega; 3, 16-bit pc; 4, 22-bit pc.
Fixed accordingly.
modified: sim/sim_core.c
Merge pull request #64 from bsekisser/master-core-regmacro-descript
sim_core: reworked register macros and descriptor lines
Merge pull request #65 from cardoe/gdb-stub-update
Add some commands to the GDB stub
gdb: support reporting memory map locations
GDB wants to have knowledge of the RAM and flash regions of memory on
the chips. Since AVR is Harvard architecture, the RAM must begin at a
fake offset and per Atmel's docs that is 0x800000.
gdb: support qOffsets command
GDB will ask what offsets should be applied to the the text and data
sections. Since AVR is Harvard architecture so we need to apply an
offset for one of the regions universally, Atmel documents and uses
0x800000 for RAM so this makes that happen.
gdb: support qAttached command from debugger
When using avr-gdb on Ubuntu 12.04, this command is always sent
and we responded as if it was unsupported. Unfortunately avr-gdb on
Ubuntu 12.04 crashes when detaching from the process because it makes a
bad assumption somewhere, this will prevent the crash.
sim_core: reworked register macros and descriptor lines
reworked register macros and instruction descriptor lines to more
closely follow avr data sheet insruction (and avr instruction wiki)
references. register macro usage (with few exceptions) have been worked
throughout the core to be more uniform and consistent. most notably d
is used nearly uniform throught the avr instruction set references,
prior the core intermixed the usage of the opcode registers d and r
notation.
lpm & elpm, trace bug fixed... tracing would always show lpm Z+ regardless of
the actual operation performed... more importantly than that, looking
at the instruction data sheet reference, the relevant bit is bit 1
in the opcode... prior op was equal to opcode & 3 similar to ld/st
instructions... the original lpm checked for op == 1 and the
reworked elpm checked for op == 3. this has been corrected for
both opcode implimentations by setting op to opcode & 1 and just
using op to flag for post increment.
modified: sim/sim_core.c
Merge pull request #63 from cardoe/flash-rampz-rww
Add support for a RWW section and fix problems with flashing and using RAMPZ
flash: add support for RWWSRE/RWWSB bits in SPMCR
The Self Program Memory Control Register (SPMCR) has a bit for enabling
the read while write section (RWWSRE). This is also used for clearing
the temporary page buffer that is used for page writing (PGWRT). The
read while write section busy (RWWSB) allows the application developer
to know when the RWW section is accessible and when programming of it
has completed.
This commit does not wire up the behavior but just allows the flash
structure to understand that it supports a RWW section.
megax8: Add missing define before including AVR hdr
mega48, mega88, and mega168 all share a common header and rely on their
platform to be defined prior to their headers being included.
16-bits is not large enough if using RAMPZ
The RAMPZ register allows the effective address to be up to 24-bit,
so a 16-bit variable is not large enough to hold it.
Support looking up the AVR_ROOT in /usr/local/avr
Merge pull request #61 from cardoe/pc-crash
Don't crash if PC is past the end of the flash section
core: set reasonably safe default for 'codeend'
Its reasonably safe to assume that 'codeend' can not be past 'flashend'
so that's a good default value.
core: don't crash if pc is past flash
If we somehow had bad code that pointed us past the end of the flash it
would segfault simavr rather than catching the bad case, this fixes and
that wraps the check in an unlikely() branch hint since its very
unlikely we will take that case.
add likely/unlikely branch hint macros
Provide likely/unlikely branch hinting macros.
vcd: Traces now start in 'X' state
"Floating" state, until they are explicitely set by the firmware or
emulator
Signed-off-by: Michel Pollet <buserror@gmail.com>
ioport: Add a pair of IRQs
Allows easy tracking of the PORT/PIN (when read) and DDR values as they
are written by the firmware.
Also reformatted in '2014' narrow style
Signed-off-by: Michel Pollet <buserror@gmail.com>
ELF: Make sure the macro generater the correct value
You could pass constants over 8 bits in size, generating very confusing
values
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #60 from bsekisser/avr-timer-cancel-timer-rollup
avr_timer: roll up cancelation of timers into single function.
avr_timer: roll up cancelation of timers into single function.
modified: sim/avr_timer.c
Merge pull request #59 from bsekisser/ld-st-rXYZ-bugfix
sim_core: Fix for issue #46, correction to ld {rXYZ}
cores: Fix mega2560
Added EIND, as per nnayo's. Also renamed the file to match the other
cores
Signed-off-by: Michel Pollet <buserror@gmail.com>
test: Fix coroutine on old gcc
Removed traling colon. Fix issue #34
Signed-off-by: Michel Pollet <buserror@gmail.com>
make: Allow override of root path
Allows inclusion of Makefile.common from out of tree.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #53 from nnayo/gdb_fault
fix gdb error message: Cannot remove breakpoints because program is no l...
Merge pull request #45 from cardoe/prototype-warning
Fix avr_global_logger_get() decl to not warn.
Fix avr_global_logger_get() decl to not warn
When using sim_avr.h with a project that uses -Wstrict-prototypes, you
will get a warning that the prototype for avr_global_logger_get() is not
valid. Functions that take no args must explicitly use void to not warn.
Merge pull request #56 from bsekisser/avr-timer-comp-write-ocr
avr_timer: changed avr_timer_write_ocr as part of larger avr_timer refac...
avr_timer: changed avr_timer_write_ocr as part of larger avr_timer refactor.
- changed avr_timer_write_ocr code to take pointer of relevant
comparator structure rather than its parent timer.
- added _timer_get_comp_ocr which the modified avr_timer_write_ocr
function uses.
modified: simavr/sim/avr_timer.c
modified: simavr/sim/avr_timer.h
Merge pull request #54 from bsekisser/uart-udr-write-changes
uart: refactor uart udr write operation outside generic uart write.
core: Handle EIND register
Parts with more than 128KB of flash need an extra byte on the stack
Rework from nnayo branch for the atmega2560
Signed-off-by: Michel Pollet <buserror@gmail.com>
core: Removed trace crash macro
Made it a function instead.
Reworked from nnayo's commit
uart: refactor uart udr write operation outside generic uart write.
modified: simavr/sim/avr_uart.c
fix gdb error message: Cannot remove breakpoints because program is no longer writable.
Merge pull request #50 from cardoe/atmega128rfa1
cores: add ATmega128RFA1 core
timers: Reformat
Cleanup the macros
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: add ATmega128RFA1 core
This core is based on the ATmega1281 core per Atmel's documentation so
that was used as a starting point. No guarentees that the radio is wired
up correctly.
timers: Real fix
There were a couple of logic error in the previous commit, fixed,
hopefully.
simduino: Small fix
Not sure how this got commited, it was not compiling.
timers: New, faster implementation
Bullied by bsekisser into making this one ;-)
Signed-off-by: Michel Pollet <buserror@gmail.com>
gdb: cleanup
Formatting, nothing functional.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #39 from ppd1990/makefile-threaded
Make Makefile safe for parallel compilation.
sim_core: correction to ld {rXYZ}
User supplied test seems to indicate that the avr writes data to
the destination register AFTER updating the index register.
whereas the core originally read the index register and
immediately stored the result into the register and then wrote
back the index register.
If the code used: LD XH, X test indicated XH would return the
value loaded from the indirect load operation versus the updated
XH:XL value as the core originally assumed.
modified: sim/sim_core.c
Merge pull request #43 from cardoe/special-init-api
Extend special_init/special_deinit API
Extend special_init/special_deinit API
Its pretty common for callback style APIs to include a private pointer
to allow the user to pass in contextual data through the callback API
(see pthread_create for an example). This change adds that for
special_init() and special_deinit() which are designed as callbacks.
Effectively this behavior was used in the only two examples that used
those callbacks by having global variables, however globals are of
limited use for programs that might instantiate multiple avr cores.
Merge pull request #41 from nnayo/segfault
correct a segfault
Merge pull request #42 from nnayo/typo
fix typo
Make Makefile safe for parallel compilation.
Merge pull request #38 from ppd1990/megax-timer
Fix timer0 on megax MCUs. Stick to lowest common denominator (atmega8) i...
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