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core: Added a new ELF tag with AVR->simavr command path
This new mode allow the AVR firmware to specify an (unused)
AVR IO register as a "command path" to send commands back to
simavr.
It allows for example the firmware to start/stop the VCD trace
dump, exactly where it should from the ooint of view of the
firmware being ran.
See atmega88_uart_echo.c for an example.
Signed-off-by: Michel Pollet <buserror@gmail.com>
comments: What don't you typo the comments, too ?
Fixed a few!
Signed-off-by: Michel Pollet <buserror@gmail.com>
timer: Implemented some of the ICR based timers
Also made a PWM and a Fast PWM mode. Fast pwm doesm't use the
interrupts, as most of the time it's never used. Aldo it kills
performanves when calling a timer every 400 cycles.
Signed-off-by: Michel Pollet <buserror@gmail.com>
misc: Disabled debug traces
No functionsl changes
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: Also disable fuse macros
For silly ubuntu
Signed-off-by: Michel Pollet <buserror@gmail.com>
timers: Added TCNT reading/writing support
TCNT read/write is now working. It is recalculated at read time.
You can also write to it to reset the timer to a fixed value, this resets
the simavr timer base accordingly.
Note that some timer modes should /not/ let the AVR write to TCNT, this
is not handled right now.
Also added an example of AVR code that uses timers, change TCNT1 and
generates a nice trace file with all the changes.
Signed-off-by: Michel Pollet <buserror@gmail.com>
IRQ: Made the hook structure private
No functional changes
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: Disable signatures to help compile on ubuntu
Ubuntu and gento uses old avr toolchain, that lacks
the SIGNATURE defines.
So I disabled it in simavr, it was not used for
anything functional for now anyway
Signed-off-by: Michel Pollet <buserror@gmail.com>
examples: Minor updates
New timers etc...
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: Added ATTiny2313
Another new core...
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: Updated for 16 bits timers and ADCs
Also made a macro for EXTINT declarations.
Signed-off-by: Michel Pollet <buserror@gmail.com>
ADC: Placeholder IO module
Not doing anything for now, but the IO blocks are filled
in the core definitiond already.
Signed-off-by: Michel Pollet <buserror@gmail.com>
timer: Masssive timer update. 8 & 16 bits
Re-massaged the timer code. It now works as 8 or 16 bits,
Also added a way to soecify the mode the timer run, and made
the TOV, COMPA and COMPB work as they should.
Now support the "Normal" timer mode too.
Signed-off-by: Michel Pollet <buserror@gmail.com>
README an Makefiles update
Makefiles for the examples should work in ubuntu
Signed-off-by: Michel Pollet <buserror@gmail.com>
timer_64led: Brand new example board, opengl display too
This example is a real board firmware that was built and
works. The firmware was adapted lightly and now runs
perfectly in simavr. It's a "stopwatch" timer with a lot
of features.
The "board" generates a very complete waveform for a LOT
of interesting signals, like the 74HC595 latches, intetupts,
SPI activity and the lot.
This example is the crown jewel of simavr development so far,
because simavr was design with the goal of being able to simulate
one's own project, for real.
Signed-off-by: Michel Pollet <buserror@gmail.com>
ledramp: Use a larger VCD update window
No longer needs a 5usec window, the timer does the job
Signed-off-by: Michel Pollet <buserror@gmail.com>
Makefiles: Small updates
For consistency only...
Signed-off-by: Michel Pollet <buserror@gmail.com>
ELF: Use a much larger VCD flush window
With the new log VCD handling, a much larger timeout is
perfectly fine.
Signed-off-by: Michel Pollet <buserror@gmail.com>
VCD: Reworked
More or less re-did the VCD handling, now ues a "log" of signal
changes instead of a timeslice. The log is flushed at regular
interval using a timer.
The log also handles signal changes that are smaller than one usec
(the minimum time slice in our VCD).
Signed-off-by: Michel Pollet <buserror@gmail.com>
interrupts: Added a "raised" IRQ
Added a "raise" IRQ that is set to 1 when the interrupt is
scheduled, and to 0 when the handler is called.
This allows the interrupts to be traced into a VCD file
waveform, amongst other things.
Signed-off-by: Michel Pollet <buserror@gmail.com>
core: Reworked the cycle timers
Ensure that a timer when called does not continue to have a
"call next" that is smaller than the current cycle, bogging
down the rest of the core.
Also ensure the cycle is always incremented by at least one
when sleeping, even if a cycle callback is called.
Signed-off-by: Michel Pollet <buserror@gmail.com>
core: Added an avr_terminate() call
This allow the VCD file to be flushed and closed properly.
Signed-off-by: Michel Pollet <buserror@gmail.com>
uart: Register the interupt vectors
This has no functiinal change, apart to keep the table of
"handled" interupts in the avr_t structure complete.
Signed-off-by: Michel Pollet <buserror@gmail.com>
timer8: Implements "fast PWM" mode
Added IRQs that outputs the PWM duty cycle when changed
by the AVR code.
Signed-off-by: Michel Pollet <buserror@gmail.com>
spi: Use a timer to send the bytes out, when master
No longer output the bytes too fast, that could create collisions
with the SPI in IRQ.
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: Add a few more mega cores
Added mega164, mega324, mega328
Signed-off-by: Michel Pollet <buserror@gmail.com>
Fixed 'ledramp' example to reflect new loader
No functional changes
Signed-off-by: Michel Pollet <buserror@gmail.com>
ELF: Updated example firmware to generate new traces
Example firmware declares two traces that will generate a
trace file automaticaly when run with run_avr. The file is
created at load time using the .mmcu declarations.
Signed-off-by: Michel Pollet <buserror@gmail.com>
ELF: Redone the .mmcu section
The section now uses :tags: that can be parsed regardless
of order, size, alignment and so on.
Also added tags to allow a firmware to register VCD traces
directly from macros placed in the firmware itself.
This allows very quick and painless trace generation of any IO
register/bit without having to know the real values for the
addresses.
Signed-off-by: Michel Pollet <buserror@gmail.com>
VCD: Traces now have the correct timestamps
Traces in multiple of the "period" and use the
correct stamps for value changes.
Signed-off-by: Michel Pollet <buserror@gmail.com>
UART: Delay TX interupt a few cycles
Also clear the "buffer empty" flag when UDR is written
Signed-off-by: Michel Pollet <buserror@gmail.com>
Added support for IRQ triggers on any IO register
Each IO address has it's own IRQ list now, dynamicaly
allocated when needed. It allows any code to register
an IRQ callback for any change made to any register.
Even registers that have no IO drivers (yet?) can be
monitored.
As a silver lining, this means any register or register bit
can be traced in a VCD file and displayed in gtkwave.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Added support for external interrupts (ie INT0 etc)
Small module to implement the INT0 .. INT3 interrupts.
These hook up in ioport pin IRQs to trigger the
vectors.
Added vectors for the existing cores.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Missing bits from previous commit...
Key maps etc..
Signed-off-by: Michel Pollet <buserror@gmail.com>
Updated "ledramp" to demo the VCD gtkwave traces
This patch is all that is needed to allow the demo "board"
to dump a file that will display graphicaly in gtkwave.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Adds VCD (Value Change Dump) file output support (gtkwave)
This subsystem is not called by the core itself, it is
an utility available to other "boards".
Allows the simulator to dump graphical traces readable
in gtkwave.
The subsystem allows any number of trace files in parallel,
any sampling periods, and a maximum of 32 traces per file.
See updated "ledramp.c" example for a very simple way to use
the code.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Streamlined avr_irq subsystem
Made the IRQ subsytem even more generic, allows
IRQs to be directly connected to other IRQ without
the glue callback.
Also added flags to allow changing IRQ polarity, and
to enable/disable a "filter" that won't trigger the
callbacks when the IRQ value is the same as before.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Disable the debugging traces
Added a (Disabled by default) compile flag for the
heavy-duty debugger that helped debug the core. No
longer needed in full builds since 1) it works
2) gdb works for user code..
Signed-off-by: Michel Pollet <buserror@gmail.com>
Cleanup of the Makefiles
General cleanup, updated comments
Signed-off-by: Michel Pollet <buserror@gmail.com>
Added a real example on how to integrate simavr, etc
+ OpenGL app loads, runs a firmware and interacts with it.
See the README in examples/ledramp
+ Updated Makefiles & Readme
Streamlined the makefiles, so they use the Makefile.common
rules and so on. Also updated README to bring it up to date.
+ Adding TWI - work in progress
Non working implementation skeleton. Defines a "slave" and a "bus"
And the AVR twi interface that has one of each
Signed-off-by: Michel Pollet <buserror@gmail.com>
Added a typedef for IO addresses
Used to be 8 bits only in the code, but bit megas use 9 bits,
so the new type is uint16_t.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Added tiny13
And macros to declare eeprom with 8 bits address.
Signed-off-by: Jon Escombe <lists@dresco.co.uk>
Signed-off-by: Michel Pollet <buserror@gmail.com>
Many more changes, timed callbacks etc
Now have functions to convert from/to cycles & usecs, use them for
implementing the new "one shot" timer callbacks.
IO modules now use "one shots" to implement "call later" subsystems,
like eeprom, uart, timers and so on.
Signed-off-by: Michel Pollet <buserror@gmail.com>
tiny25/45 cores added
Same method as the mega48/88/168...
Signed-off-by: Jon Escombe <lists@dresco.co.uk>
Signed-off-by: Michel Pollet <buserror@gmail.com>
Polished gdb support, etc
GDB handler re-done, removed the thread, removed the pauses,
Now as fast as possible for stepping trhu code.
Note you /need/ the dwarf-2 debug symbols for gdb to work
properly, a simple '-g' will not work.
Also added a mode that starts the gdb server and waits if the
AVR core detects a "crash". Added a piece if test unit to
test just that.
Signed-off-by: Michel Pollet <buserror@gmail.com>
GDB working, some more source massaging
Big news is gdb support, you can trace, breakpoint,
resume, inspect (including eeprom addresses!).
You can't modify variables on the fly yet.
It's not very fast rignt now, but some very obvious
changes will help that a lot.
Other changes are more moving, shuffling. "simavr"
is gone, replaced by a simple "run_avr" that does
the same, but no longer has any emulation specific
code.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Build works on Snow Leopard, using Arduino toolchain
Tried the make system on Snow Leopard with a change in the
Makefiles to go and get avr-gcc and such in the Arduino.app
bundle.
Also fixed the .mmcu ELF header to be compatible with x86_64
Signed-off-by: Michel Pollet <buserror@gmail.com>
uart, ioports, etc. Many more changes
+ Reorganized source, split simavr.c
+ IRQ support added to IO modules
+ timer8: fixed a bug related to disabling clock
+ uart:
- Added support for txen/rxen flags
- Added a receive fifo, and the rx interupt
- added a "atmega88_uart_echo" test case
+ simavr: hook rx & tx irqs on first uart, for tests
Signed-off-by: Michel Pollet <buserror@gmail.com>
Cores, decoder, uart, ioports - lots of changes
+ Cores now use eeprom declare macro
+ Cores now use the "TXCE" etc bits
+ Uart now raise TXC interupt/flag
+ ioports now use new internal IRQ system
+ New command line options for mcu, freq and trace
+ Decoder updates:
- Fixed the last known "crash" bug.
- Added cycles to most multi-cycle opcodes.
- Added optional stack frame watcher
- Skip instruction now handle 32 bits skips
Signed-off-by: Michel Pollet <buserror@gmail.com>
Initial Commit
Signed-off-by: Michel Pollet <buserror@gmail.com>
projects / sx / simavr.git / log