parts: Bug fix for i2c_eeprom part
Fixes:
> Part address and mask weren't set in i2c_eeprom_init. The
virtual part responded to all addresses.
> Mask required inverting to function as per the description in
i2c_eeprom.h
examples: Added SSD1306 example board
atmega32_ssd1306.c Example avr firmware
ssd1306.* SSD1306 avr driver
images.* simavr logo used in example firmware
ssd1306demo.c simavr demo for ssd1306 part
parts: Added SSD1306 OLED driver virtual part
Merge pull request #73 from cardoe/rfa1-rfr2-pcint8
cores: Fix PCINT8 for ATmega128RFA1 and ATmega128RFR2
cores: Fix PCINT8 for ATmega128RFA1 and ATmega128RFR2
PCINT8 was previously not setup. Per the spec sheet it is on Port E pin
0.
Merge pull request #72 from cardoe/rfr2
Support for ATmega128RFR2
cores: RFA1/RFR2 don't have Port A and Port C
The ATmega128RFA1 and ATmega128RFR2 don't actually have Port A and Port
C as IO pins.
cores: Add initial support for ATmega128RFR2
Add initial support for the ATmega128RFR2 which according to Atmel is a
drop in replacement for the ATmega128RFA1 however in real world testing
I have found this to not be entirely true. All of the changes (new
features) added to the R2 are not exposed with current simavr
peripherals so this file is identical to the A1 in simavr.
Clean up outdated comment
This comment is no longer true for any of the listed platforms so its
best to adjust the wording to what might be relevant to users
cores: Fix ADCH and ADCL to use defines for RFA1
No current release provides these defines however they are fixed in
avr-libc trunk and as such we should use them if they are available.
Merge pull request #71 from bsekisser/master-core-fixes-reductions
sim_core: fixes and reductions
sim_core: fixes and reductions
correct a few goofed up opcode descriptions.
get_d5 and get_r5: remove trailing slash on last macro line
add get_vd5: get_vd5 pulls in from get_d5 plus loads from register...
removes one definate instance of a possible double load, also
potentially removes double loads during tracing.
get_d5_b3 changed to get_vd5_b3: as all instances use the value of
reg d. get_vd5_b3 pulls in from get_vd5. reduces one definate
instance for potential of double loads and possibly reducing
the potential during tracing.
add get_vd5_b3_mask: two instances use b3 as a mask, get_vd5_b3_mask
pulls in from get_vd5_b3.
add get vh4_k8: get_vh4_k8 pulls in from get_h4_k8, removes the extra
line to pull in from the register... removes possible double
load during tracing.
get_p2_k6 changed to get_vp2_k6: register load was moved into the macro
as both instances need the value loaded from the register pair.
add get_io5 and get_io5_b3mask: get io5_b3 and get_io5_b3mask pulls in
from get_io5... most instances using get_io5_b3 take bit
number and use it as a mask, get_io5_b3mask does that by default.
get_o12: rcall and rjmp both left shift the value back before using
the offset... the macro just calls for one less bit to be
shifted... during trace we then make the extra shift as needed.
modified: sim/sim_core.c
Merge pull request #67 from bsekisser/master-core-refactor-flags
sim_core: flag equations refactored.
Merge pull request #69 from bsekisser/master-core-ldi-labeling-misc
sim_core: add ldi, trace and labeling corrections.
sim_core: flag equations refactored.
Most flag equations have been refactored into flag group function
blocks... The core passes all provided tests in the tests folder
and now most especially is able to pass the instruction test code.
At the same time, the overall average cycles per instruction has
ticked down.
modified: sim/sim_core.c
sim_core: add ldi, labeling corrections.
in moving the majority of instructions to follow use of register
macros, ldi was missed.
get_h4_k16() was incorrectly labeled where get_h4_k8() was intended
as k is an 8 bit quantity not 16.
get_o_12() was changed to get_o12() following the convention set
forth with the other macros.
several trace statements were missed during the conversion and fixed.
ORI was incorrecly labeled as ANDI in the description and corrected.
modified: sim/sim_core.c
Merge pull request #68 from bsekisser/master-core-fix-rcall-cycles
sim_core: fix rcall instruction cycles...
sim_core: fix rcall instruction cycles...
Based on the instrtiming.elf code and checking the Avr Instruction
Manual, RCALL was found to be producing incorrect cycle counts.
Atmega; 3, 16-bit pc; 4, 22-bit pc.
Fixed accordingly.
modified: sim/sim_core.c
Merge pull request #64 from bsekisser/master-core-regmacro-descript
sim_core: reworked register macros and descriptor lines
Merge pull request #65 from cardoe/gdb-stub-update
Add some commands to the GDB stub
gdb: support reporting memory map locations
GDB wants to have knowledge of the RAM and flash regions of memory on
the chips. Since AVR is Harvard architecture, the RAM must begin at a
fake offset and per Atmel's docs that is 0x800000.
gdb: support qOffsets command
GDB will ask what offsets should be applied to the the text and data
sections. Since AVR is Harvard architecture so we need to apply an
offset for one of the regions universally, Atmel documents and uses
0x800000 for RAM so this makes that happen.
gdb: support qAttached command from debugger
When using avr-gdb on Ubuntu 12.04, this command is always sent
and we responded as if it was unsupported. Unfortunately avr-gdb on
Ubuntu 12.04 crashes when detaching from the process because it makes a
bad assumption somewhere, this will prevent the crash.
sim_core: reworked register macros and descriptor lines
reworked register macros and instruction descriptor lines to more
closely follow avr data sheet insruction (and avr instruction wiki)
references. register macro usage (with few exceptions) have been worked
throughout the core to be more uniform and consistent. most notably d
is used nearly uniform throught the avr instruction set references,
prior the core intermixed the usage of the opcode registers d and r
notation.
lpm & elpm, trace bug fixed... tracing would always show lpm Z+ regardless of
the actual operation performed... more importantly than that, looking
at the instruction data sheet reference, the relevant bit is bit 1
in the opcode... prior op was equal to opcode & 3 similar to ld/st
instructions... the original lpm checked for op == 1 and the
reworked elpm checked for op == 3. this has been corrected for
both opcode implimentations by setting op to opcode & 1 and just
using op to flag for post increment.
modified: sim/sim_core.c
Merge pull request #63 from cardoe/flash-rampz-rww
Add support for a RWW section and fix problems with flashing and using RAMPZ
flash: add support for RWWSRE/RWWSB bits in SPMCR
The Self Program Memory Control Register (SPMCR) has a bit for enabling
the read while write section (RWWSRE). This is also used for clearing
the temporary page buffer that is used for page writing (PGWRT). The
read while write section busy (RWWSB) allows the application developer
to know when the RWW section is accessible and when programming of it
has completed.
This commit does not wire up the behavior but just allows the flash
structure to understand that it supports a RWW section.
megax8: Add missing define before including AVR hdr
mega48, mega88, and mega168 all share a common header and rely on their
platform to be defined prior to their headers being included.
16-bits is not large enough if using RAMPZ
The RAMPZ register allows the effective address to be up to 24-bit,
so a 16-bit variable is not large enough to hold it.
Support looking up the AVR_ROOT in /usr/local/avr
Merge pull request #61 from cardoe/pc-crash
Don't crash if PC is past the end of the flash section
core: set reasonably safe default for 'codeend'
Its reasonably safe to assume that 'codeend' can not be past 'flashend'
so that's a good default value.
core: don't crash if pc is past flash
If we somehow had bad code that pointed us past the end of the flash it
would segfault simavr rather than catching the bad case, this fixes and
that wraps the check in an unlikely() branch hint since its very
unlikely we will take that case.
add likely/unlikely branch hint macros
Provide likely/unlikely branch hinting macros.
vcd: Traces now start in 'X' state
"Floating" state, until they are explicitely set by the firmware or
emulator
Signed-off-by: Michel Pollet <buserror@gmail.com>
ioport: Add a pair of IRQs
Allows easy tracking of the PORT/PIN (when read) and DDR values as they
are written by the firmware.
Also reformatted in '2014' narrow style
Signed-off-by: Michel Pollet <buserror@gmail.com>
ELF: Make sure the macro generater the correct value
You could pass constants over 8 bits in size, generating very confusing
values
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #60 from bsekisser/avr-timer-cancel-timer-rollup
avr_timer: roll up cancelation of timers into single function.
avr_timer: roll up cancelation of timers into single function.
modified: sim/avr_timer.c
Merge pull request #59 from bsekisser/ld-st-rXYZ-bugfix
sim_core: Fix for issue #46, correction to ld {rXYZ}
cores: Fix mega2560
Added EIND, as per nnayo's. Also renamed the file to match the other
cores
Signed-off-by: Michel Pollet <buserror@gmail.com>
test: Fix coroutine on old gcc
Removed traling colon. Fix issue #34
Signed-off-by: Michel Pollet <buserror@gmail.com>
make: Allow override of root path
Allows inclusion of Makefile.common from out of tree.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #53 from nnayo/gdb_fault
fix gdb error message: Cannot remove breakpoints because program is no l...
Merge pull request #45 from cardoe/prototype-warning
Fix avr_global_logger_get() decl to not warn.
Fix avr_global_logger_get() decl to not warn
When using sim_avr.h with a project that uses -Wstrict-prototypes, you
will get a warning that the prototype for avr_global_logger_get() is not
valid. Functions that take no args must explicitly use void to not warn.
Merge pull request #56 from bsekisser/avr-timer-comp-write-ocr
avr_timer: changed avr_timer_write_ocr as part of larger avr_timer refac...
avr_timer: changed avr_timer_write_ocr as part of larger avr_timer refactor.
- changed avr_timer_write_ocr code to take pointer of relevant
comparator structure rather than its parent timer.
- added _timer_get_comp_ocr which the modified avr_timer_write_ocr
function uses.
modified: simavr/sim/avr_timer.c
modified: simavr/sim/avr_timer.h
Merge pull request #54 from bsekisser/uart-udr-write-changes
uart: refactor uart udr write operation outside generic uart write.
core: Handle EIND register
Parts with more than 128KB of flash need an extra byte on the stack
Rework from nnayo branch for the atmega2560
Signed-off-by: Michel Pollet <buserror@gmail.com>
core: Removed trace crash macro
Made it a function instead.
Reworked from nnayo's commit
uart: refactor uart udr write operation outside generic uart write.
modified: simavr/sim/avr_uart.c
fix gdb error message: Cannot remove breakpoints because program is no longer writable.
Merge pull request #50 from cardoe/atmega128rfa1
cores: add ATmega128RFA1 core
timers: Reformat
Cleanup the macros
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: add ATmega128RFA1 core
This core is based on the ATmega1281 core per Atmel's documentation so
that was used as a starting point. No guarentees that the radio is wired
up correctly.
timers: Real fix
There were a couple of logic error in the previous commit, fixed,
hopefully.
simduino: Small fix
Not sure how this got commited, it was not compiling.
timers: New, faster implementation
Bullied by bsekisser into making this one ;-)
Signed-off-by: Michel Pollet <buserror@gmail.com>
gdb: cleanup
Formatting, nothing functional.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #39 from ppd1990/makefile-threaded
Make Makefile safe for parallel compilation.
sim_core: correction to ld {rXYZ}
User supplied test seems to indicate that the avr writes data to
the destination register AFTER updating the index register.
whereas the core originally read the index register and
immediately stored the result into the register and then wrote
back the index register.
If the code used: LD XH, X test indicated XH would return the
value loaded from the indirect load operation versus the updated
XH:XL value as the core originally assumed.
modified: sim/sim_core.c
Merge pull request #43 from cardoe/special-init-api
Extend special_init/special_deinit API
Extend special_init/special_deinit API
Its pretty common for callback style APIs to include a private pointer
to allow the user to pass in contextual data through the callback API
(see pthread_create for an example). This change adds that for
special_init() and special_deinit() which are designed as callbacks.
Effectively this behavior was used in the only two examples that used
those callbacks by having global variables, however globals are of
limited use for programs that might instantiate multiple avr cores.
Merge pull request #41 from nnayo/segfault
correct a segfault
Merge pull request #42 from nnayo/typo
fix typo
Make Makefile safe for parallel compilation.
Merge pull request #38 from ppd1990/megax-timer
Fix timer0 on megax MCUs. Stick to lowest common denominator (atmega8) i...
Fix timer0 on megax MCUs. Stick to lowest common denominator (atmega8) in terms of functionality.
Merge pull request #37 from ppd1990/atmega-icp
Correctly set timer1's ICP on atmega8, atmega16 and atmega32.
Correctly set timer1's ICP on atmega8, atmega16 and atmega32.
cores: m16 and m32 fix
Core struct declaration had a problem when the 'porta' was not declared.
Now declare it last, so it doesnt clash anymore.
core: renamed MCU section variable name
This was clashing with the command register
Signed-off-by: Michel Pollet <buserror@gmail.com>
uart_pty: Fix the race condition
There had been a race condition in there for a rather long while,
I've finaly tracked it down to a small idiotic change of trying to
flush a buffer from the wrong thread.
Removing that flush makes it works properly as intended, without the
mutex.
Signed-off-by: Michel Pollet <buserror@gmail.com>
twi: Fix a clang error
clang doesn't like unused static functions at all.
Signed-off-by: Michel Pollet <buserror@gmail.com>
fifo: cleaned warnings and removed volatile
Should not need the volatile declaration anymore.
Also use the "unused" designation to prevent clang to complain
about unused static functions.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge remote-tracking branch 'thomasa88/feature/detect_avr_root' into dev-home
cores: Added atmega1284.c
That one has an extra timer, it seems.
Signed-off-by: Michel Pollet <buserror@gmail.com>
spi: Clear SPIF when writing to SPDR
The manual says the SPIF bit is cleared when accessing (i.e. reading _or_
writing) the SPDR register after an interrupt is raised. By clearing SPIF
on a write to SPDR, the following code starts to work:
SPDR = 0xff; loop_until_bit_is_set (SPSR, SPIF);
SPDR = 0x00; loop_until_bit_is_set (SPSR, SPIF);
(where the bytes are arbitrarily chosen). This didn’t work before as the
SPIF bit wasn’t cleared by the second write to SPDR, so the second loop
turned into a no-op. This caused the write timer for the first byte to be
overwritten by the write timer for the second. Consequently, the first byte
never got transmitted.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge remote-tracking branch 'pwithnalls/warning-fixes' into dev-home
core: Declare avr_pending_sleep_usec
This was meant to be declared for 'boards' to use
Signed-off-by: Michel Pollet <buserror@gmail.com>
timer: Tweak traces
Display the period in uS as well as cycles
Signed-off-by: Michel Pollet <buserror@gmail.com>
Makefile: Test multiple AVR roots for Linux and error out if none found
Inspired by thors@github.
This should find correct paths for at least Arch, Debian, Fedora, Gentoo, OpenSUSE, Ubuntu.
avr: Make vector trace work
Somehow the vector list was erased at avr_reset time, luckily only the
trace code in run_avr was using it.
Signed-off-by: Michel Pollet <buserror@gmail.com>
simavr: Removed the avr_global_logger global
It was not very clean; Instead there is a new accessor for
setting/getting a global logging function pointer.
Also made sure it is not compiled for the cores, since they use AVR
headers and have no stdarg.h anyway
Signed-off-by: Michel Pollet <buserror@gmail.com>
core: Fix a possible buffer overrun
From bsekisser@github
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: Added mega16
No idea why it wasn't there already. Uncommon part.
Signed-off-by: Michel Pollet <buserror@gmail.com>
cores: Added PORTA to atmega32
Inspired by sealibora@github
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #33 from bsekisser/uart-u2x-bugfix
avr_uart.c: fix to prevent overwriting readonly flags when setting u2x.
avr_uart.c: fix to prevent overwriting readonly flags when setting u2x.
modified: simavr/sim/avr_uart.c
tests: Added a coroutine example
Slapped together test, but demonstrates a nice trick that works
on AVR for havbing multiple tasks concurently (coorperatively)
Signed-off-by: Michel Pollet <buserror@gmail.com>
mmcu: Tweak to the macros to allow multiple declarations
This trick adds the line number in the declaration of the fake
'variable' to allows multiple declarations to coexists, it is used
for the pullup/down declaration in particular
Signed-off-by: Michel Pollet <buserror@gmail.com>
Merge pull request #30 from bsekisser/sim-core-muls-bugfix
sim_core.c: fix implimentation of muls instruction
Merge pull request #29 from bsekisser/sim-core-ror-bugfix
sim_core.c: fix implimentation of ror instruction
Merge pull request #28 from bsekisser/sim-core-bld-bugfix
sim_core.c: fix implimentation of bld instruction
Merge pull request #27 from bsekisser/sim-core-inc-dec-bugfix
sim_core.c: fix implimentation of inc/dec to match specification
sim_core.c: fix implimentation of muls instruction
specification for muls insruction states 2 cycles, not one as implimented.
bug find credit goes to: Shay Green <gblargg@gmail.com>
modified: sim_core.c
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