From 29a85763db634ae914e808714cd2b4c6e310bb66 Mon Sep 17 00:00:00 2001
From: Michel Pollet <buserror@gmail.com>
Date: Thu, 1 Oct 2015 15:07:54 +0100
Subject: [PATCH] cores: Added support for mega324a / pa..

Support for the renamed SPI block, somehow my headers (debian) don't
have any definition of a second one, but, the macro /should/ support it
now.

Signed-off-by: Michel Pollet <buserror@gmail.com>
---
 simavr/cores/sim_mega324.c  | 14 +++++++++++--
 simavr/cores/sim_mega324a.c | 42 +++++++++++++++++++++++++++++++++++++
 simavr/cores/sim_megax4.h   |  4 ++++
 simavr/sim/avr_spi.h        | 23 ++++++++++++++++++++
 4 files changed, 81 insertions(+), 2 deletions(-)
 create mode 100644 simavr/cores/sim_mega324a.c

diff --git a/simavr/cores/sim_mega324.c b/simavr/cores/sim_mega324.c
index 7c29ae0..bc74ea4 100644
--- a/simavr/cores/sim_mega324.c
+++ b/simavr/cores/sim_mega324.c
@@ -26,7 +26,17 @@
 
 #define _AVR_IO_H_
 #define __ASSEMBLER__
-#include "avr/iom324.h"
+#include "avr/iom324p.h"
+
+/* borken avr-libc missing these declarations :/ */
+/* The one from 324a are also wrong, like, I'm embarassed for whomever
+ * put that in... */
+#ifndef LFUSE_DEFAULT
+#define LFUSE_DEFAULT 0 // (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
+#define HFUSE_DEFAULT 0 // (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+#define EFUSE_DEFAULT (0xFF)
+#endif
+
 // instantiate the new core
 #include "sim_megax4.h"
 
@@ -36,7 +46,7 @@ static avr_t * make()
 }
 
 avr_kind_t mega324 = {
-	.names = { "atmega324", "atmega324p", "atmega324pa" },
+	.names = { "atmega324", "atmega324p" },
 	.make = make
 };
 
diff --git a/simavr/cores/sim_mega324a.c b/simavr/cores/sim_mega324a.c
new file mode 100644
index 0000000..5ea5676
--- /dev/null
+++ b/simavr/cores/sim_mega324a.c
@@ -0,0 +1,42 @@
+/*
+	sim_mega324.c
+
+	Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
+
+ 	This file is part of simavr.
+
+	simavr is free software: you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 3 of the License, or
+	(at your option) any later version.
+
+	simavr is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with simavr.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sim_avr.h"
+
+#define SIM_MMCU		"atmega324a"
+#define SIM_CORENAME	mcu_mega324a
+
+#define _AVR_IO_H_
+#define __ASSEMBLER__
+#include "avr/iom324pa.h"
+// instantiate the new core
+#include "sim_megax4.h"
+
+static avr_t * make()
+{
+	return avr_core_allocate(&SIM_CORENAME.core, sizeof(struct mcu_t));
+}
+
+avr_kind_t mega324a = {
+	.names = { "atmega324a", "atmega324pa" },
+	.make = make
+};
+
diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index e579024..2d1abcb 100644
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -462,7 +462,11 @@ const struct mcu_t SIM_CORENAME = {
 		}
 	},
 #endif
+#ifdef MSTR0 /* xx4a and xx4pa series */
+	AVR_SPIX_DECLARE(0, PRR0, PRSPI),
+#else
 	AVR_SPI_DECLARE(PRR0, PRSPI),
+#endif
 	.twi = {
 		.disabled = AVR_IO_REGBIT(PRR0,PRTWI),
 
diff --git a/simavr/sim/avr_spi.h b/simavr/sim/avr_spi.h
index 79a1340..23ff78f 100644
--- a/simavr/sim/avr_spi.h
+++ b/simavr/sim/avr_spi.h
@@ -57,6 +57,29 @@ typedef struct avr_spi_t {
 
 void avr_spi_init(avr_t * avr, avr_spi_t * port);
 
+#define AVR_SPIX_DECLARE(_name, _prr, _prspi) \
+	.spi = { \
+		.name = '0' + _name,\
+		.disabled = AVR_IO_REGBIT(_prr, _prspi), \
+	\
+		.r_spdr = SPDR ## _name, \
+		.r_spcr = SPCR ## _name, \
+		.r_spsr = SPSR ## _name, \
+	\
+		.spe = AVR_IO_REGBIT(SPCR ## _name, SPE ## _name), \
+		.mstr = AVR_IO_REGBIT(SPCR ## _name, MSTR ## _name), \
+	\
+		.spr = { AVR_IO_REGBIT(SPCR ## _name, SPR0 ## _name), \
+					AVR_IO_REGBIT(SPCR ## _name, SPR1 ## _name), \
+					AVR_IO_REGBIT(SPSR ## _name, SPI2X ## _name) }, \
+		.spi = { \
+			.enable = AVR_IO_REGBIT(SPCR ## _name, SPIE ## _name), \
+			.raised = AVR_IO_REGBIT(SPSR ## _name, SPIF ## _name), \
+			.vector = SPI_STC_vect, \
+		}, \
+	}
+
+
 #define AVR_SPI_DECLARE(_prr, _prspi) \
 	.spi = { \
 		.disabled = AVR_IO_REGBIT(_prr, _prspi), \
-- 
2.39.5