From 382900645b1f7244d1b29cc851314c3e194c84e3 Mon Sep 17 00:00:00 2001 From: bsekisser Date: Sun, 13 Oct 2013 16:01:07 -0400 Subject: [PATCH] sim_core.c: fix implimentation of muls instruction specification for muls insruction states 2 cycles, not one as implimented. bug find credit goes to: Shay Green modified: sim_core.c --- simavr/sim/sim_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/simavr/sim/sim_core.c b/simavr/sim/sim_core.c index 03d46ff..a30cefe 100644 --- a/simavr/sim/sim_core.c +++ b/simavr/sim/sim_core.c @@ -538,6 +538,7 @@ avr_flashaddr_t avr_run_one(avr_t * avr) _avr_set_r(avr, 1, res >> 8); avr->sreg[S_C] = (res >> 15) & 1; avr->sreg[S_Z] = res == 0; + cycle++; SREG(); } break; case 0x0300: { // MUL Multiply 0000 0011 fddd frrr -- 2.39.5