From 3afc34b1802950b14e589c18f449bb07f2951c4b Mon Sep 17 00:00:00 2001 From: Doug Goldstein Date: Sun, 27 Apr 2014 15:45:34 -0500 Subject: [PATCH] cores: Add a field for Lock Bits and Boot Lock Bits Add an extra byte for allowing simavr store the chip's lock bits / boot lock bits as well as set the default value as defined in a number of specs. --- simavr/cores/sim_core_declare.h | 3 ++- simavr/sim/sim_avr.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/simavr/cores/sim_core_declare.h b/simavr/cores/sim_core_declare.h index f69e5ca..5eca3c3 100644 --- a/simavr/cores/sim_core_declare.h +++ b/simavr/cores/sim_core_declare.h @@ -78,7 +78,8 @@ .e2end = E2END, \ .vector_size = _vector_size, \ .fuse = _FUSE_HELPER, \ - .signature = { SIGNATURE_0,SIGNATURE_1,SIGNATURE_2 } + .signature = { SIGNATURE_0,SIGNATURE_1,SIGNATURE_2 }, \ + .lockbits = 0xFF #else // Disable signature when using an old avr toolchain #define DEFAULT_CORE(_vector_size) \ diff --git a/simavr/sim/sim_avr.h b/simavr/sim/sim_avr.h index cb12166..fbd15d5 100644 --- a/simavr/sim/sim_avr.h +++ b/simavr/sim/sim_avr.h @@ -152,6 +152,7 @@ typedef struct avr_t { uint8_t vector_size; uint8_t signature[3]; uint8_t fuse[6]; + uint8_t lockbits; avr_io_addr_t rampz; // optional, only for ELPM/SPM on >64Kb cores avr_io_addr_t eind; // optional, only for EIJMP/EICALL on >64Kb cores uint8_t address_size; // 2, or 3 for cores >128KB in flash -- 2.39.5