From 7a77ebb65ab202837e4713f8758f096a39c0d95a Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Wed, 10 Jan 2018 09:26:54 +0000 Subject: [PATCH] core: Added support for PC overflow Added a special opcode at the end of flash to catch PC overflow, and 'wrap it'. Also log the condition. This allow that case to be handled without having to add a modulo/division for each instruction. Signed-off-by: Michel Pollet --- simavr/sim/sim_avr.c | 3 ++- simavr/sim/sim_core.c | 7 +++++++ simavr/sim/sim_core.h | 6 ++++++ 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/simavr/sim/sim_avr.c b/simavr/sim/sim_avr.c index 1878b41..d33400a 100644 --- a/simavr/sim/sim_avr.c +++ b/simavr/sim/sim_avr.c @@ -96,8 +96,9 @@ int avr_init( avr_t * avr) { - avr->flash = malloc(avr->flashend + 1); + avr->flash = malloc(avr->flashend + 4); memset(avr->flash, 0xff, avr->flashend + 1); + *((uint16_t*)&avr->flash[avr->flashend + 1]) = AVR_OVERFLOW_OPCODE; avr->codeend = avr->flashend; avr->data = malloc(avr->ramend + 1); memset(avr->data, 0, avr->ramend + 1); diff --git a/simavr/sim/sim_core.c b/simavr/sim/sim_core.c index f3b163d..7be739b 100644 --- a/simavr/sim/sim_core.c +++ b/simavr/sim/sim_core.c @@ -1363,6 +1363,13 @@ run_one_again: case 0xf000: { switch (opcode & 0xfe00) { + case 0xf100: { /* simavr special opcodes */ + if (opcode == 0xf1f1) { // AVR_OVERFLOW_OPCODE + printf("FLASH overflow, soft reset\n"); + new_pc = 0; + TRACE_JUMP(); + } + } break; case 0xf000: case 0xf200: case 0xf400: diff --git a/simavr/sim/sim_core.h b/simavr/sim/sim_core.h index fa99638..403c119 100644 --- a/simavr/sim/sim_core.h +++ b/simavr/sim/sim_core.h @@ -129,6 +129,12 @@ static inline void avr_sreg_set(avr_t * avr, uint8_t flag, uint8_t ival) avr_sreg_set(avr, i, (src & (1 << i)) != 0); \ } +/* + * Opcode is sitting at the end of the flash to catch PC overflows. + * Apparently it's used by some code to simulate soft reset? + */ +#define AVR_OVERFLOW_OPCODE 0xf1f1 + #ifdef __cplusplus }; #endif -- 2.39.5