From bffb2e8ccbd919d058ed408ba67fbe441c17a70e Mon Sep 17 00:00:00 2001 From: Doug Goldstein Date: Sun, 27 Apr 2014 14:32:33 -0500 Subject: [PATCH] cores: Fix PCINT8 for ATmega128RFA1 and ATmega128RFR2 PCINT8 was previously not setup. Per the spec sheet it is on Port E pin 0. --- simavr/cores/sim_mega128rfa1.c | 6 ++++++ simavr/cores/sim_mega128rfr2.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/simavr/cores/sim_mega128rfa1.c b/simavr/cores/sim_mega128rfa1.c index 6904689..3a14079 100644 --- a/simavr/cores/sim_mega128rfa1.c +++ b/simavr/cores/sim_mega128rfa1.c @@ -93,6 +93,12 @@ const struct mcu_t { }, .porte = { .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE1), + .raised = AVR_IO_REGBIT(PCIFR, PCIF1), + .vector = PCINT1_vect, + }, + .r_pcint = PCMSK1, }, .portf = { .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF, diff --git a/simavr/cores/sim_mega128rfr2.c b/simavr/cores/sim_mega128rfr2.c index 63d5832..d4c8183 100644 --- a/simavr/cores/sim_mega128rfr2.c +++ b/simavr/cores/sim_mega128rfr2.c @@ -93,6 +93,12 @@ const struct mcu_t { }, .porte = { .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE, + .pcint = { + .enable = AVR_IO_REGBIT(PCICR, PCIE1), + .raised = AVR_IO_REGBIT(PCIFR, PCIF1), + .vector = PCINT1_vect, + }, + .r_pcint = PCMSK1, }, .portf = { .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF, -- 2.39.5