From c46982ae87ef5e3f1541002e4017291ded86a27c Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Thu, 9 Jan 2014 10:49:26 +0000 Subject: [PATCH] cores: Added atmega1284.c That one has an extra timer, it seems. Signed-off-by: Michel Pollet --- simavr/cores/sim_mega1284.c | 42 +++++++++++++++++ simavr/cores/sim_megax4.c | 3 ++ simavr/cores/sim_megax4.h | 92 +++++++++++++++++++++++++++++++++++-- 3 files changed, 132 insertions(+), 5 deletions(-) create mode 100644 simavr/cores/sim_mega1284.c diff --git a/simavr/cores/sim_mega1284.c b/simavr/cores/sim_mega1284.c new file mode 100644 index 0000000..375fdb0 --- /dev/null +++ b/simavr/cores/sim_mega1284.c @@ -0,0 +1,42 @@ +/* + sim_mega1284.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +#include "sim_avr.h" + +#define SIM_MMCU "atmega1284" +#define SIM_CORENAME mcu_mega1284 + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iom1284p.h" +// instantiate the new core +#include "sim_megax4.h" + +static avr_t * make() +{ + return avr_core_allocate(&SIM_CORENAME.core, sizeof(struct mcu_t)); +} + +avr_kind_t mega1284 = { + .names = { "atmega1284p", "atmega1284" }, + .make = make +}; + diff --git a/simavr/cores/sim_megax4.c b/simavr/cores/sim_megax4.c index 58500bd..54f0d96 100644 --- a/simavr/cores/sim_megax4.c +++ b/simavr/cores/sim_megax4.c @@ -41,6 +41,9 @@ void mx4_init(struct avr_t * avr) avr_timer_init(avr, &mcu->timer0); avr_timer_init(avr, &mcu->timer1); avr_timer_init(avr, &mcu->timer2); +#ifdef PRR1 + avr_timer_init(avr, &mcu->timer3); +#endif avr_spi_init(avr, &mcu->spi); avr_twi_init(avr, &mcu->twi); } diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h index 5ff74fe..a82fd3a 100644 --- a/simavr/cores/sim_megax4.h +++ b/simavr/cores/sim_megax4.h @@ -51,6 +51,9 @@ struct mcu_t { avr_uart_t uart0,uart1; avr_adc_t adc; avr_timer_t timer0,timer1,timer2; +#ifdef PRR1 + avr_timer_t timer3; +#endif avr_spi_t spi; avr_twi_t twi; }; @@ -61,6 +64,16 @@ struct mcu_t { #error SIM_MMCU is not declared #endif +/* This bit makes the PRR declaration compatible between + * all the x4 and the 'special' 1284 that has a few little + * differences + */ +#ifndef PD3 +#define PD3 PORTD3 +#define PD2 PORTD2 +#define PB3 PORTB3 +#endif + const struct mcu_t SIM_CORENAME = { .core = { .mmcu = SIM_MMCU, @@ -115,7 +128,7 @@ const struct mcu_t SIM_CORENAME = { }, .uart0 = { - .disabled = AVR_IO_REGBIT(PRR,PRUSART0), + .disabled = AVR_IO_REGBIT(PRR0,PRUSART0), .name = '0', .r_udr = UDR0, @@ -147,7 +160,7 @@ const struct mcu_t SIM_CORENAME = { }, }, .uart1 = { - .disabled = AVR_IO_REGBIT(PRR,PRUSART1), + .disabled = AVR_IO_REGBIT(PRR0,PRUSART1), .name = '1', .r_udr = UDR1, @@ -179,6 +192,7 @@ const struct mcu_t SIM_CORENAME = { }, }, .adc = { + // .disabled = AVR_IO_REGBIT(PRR0,PRADC), .r_admux = ADMUX, .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1), AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3), @@ -231,6 +245,7 @@ const struct mcu_t SIM_CORENAME = { }, .timer0 = { .name = '0', + .disabled = AVR_IO_REGBIT(PRR0,PRTIM0), .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) }, .wgm_op = { [0] = AVR_TIMER_WGM_NORMAL8(), @@ -273,7 +288,7 @@ const struct mcu_t SIM_CORENAME = { }, .timer1 = { .name = '1', - .disabled = AVR_IO_REGBIT(PRR,PRTIM1), + .disabled = AVR_IO_REGBIT(PRR0,PRTIM1), .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11), AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) }, .wgm_op = { @@ -337,6 +352,7 @@ const struct mcu_t SIM_CORENAME = { }, .timer2 = { .name = '2', + .disabled = AVR_IO_REGBIT(PRR0,PRTIM2), .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) }, .wgm_op = { [0] = AVR_TIMER_WGM_NORMAL8(), @@ -380,8 +396,74 @@ const struct mcu_t SIM_CORENAME = { } } }, +#ifdef PRR1 + .timer3 = { + .name = '3', + .disabled = AVR_IO_REGBIT(PRR1,PRTIM3), + .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31), + AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) }, + .wgm_op = { + [0] = AVR_TIMER_WGM_NORMAL16(), + [1] = AVR_TIMER_WGM_FCPWM8(), + [2] = AVR_TIMER_WGM_FCPWM9(), + [3] = AVR_TIMER_WGM_FCPWM10(), + [4] = AVR_TIMER_WGM_CTC(), + [5] = AVR_TIMER_WGM_FASTPWM8(), + [6] = AVR_TIMER_WGM_FASTPWM9(), + [7] = AVR_TIMER_WGM_FASTPWM10(), + [12] = AVR_TIMER_WGM_ICCTC(), + [14] = AVR_TIMER_WGM_ICPWM(), + [15] = AVR_TIMER_WGM_OCPWM(), + }, + .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) }, + .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */}, + + .r_tcnt = TCNT3L, + .r_tcnth = TCNT3H, + .r_icr = ICR3L, + .r_icrh = ICR3H, + + .ices = AVR_IO_REGBIT(TCCR3B, ICES3), + .icp = AVR_IO_REGBIT(PORTB, 5), + + .overflow = { + .enable = AVR_IO_REGBIT(TIMSK3, TOIE3), + .raised = AVR_IO_REGBIT(TIFR3, TOV3), + .vector = TIMER3_OVF_vect, + }, + .icr = { + .enable = AVR_IO_REGBIT(TIMSK3, ICIE3), + .raised = AVR_IO_REGBIT(TIFR3, ICF3), + .vector = TIMER3_CAPT_vect, + }, + .comp = { + [AVR_TIMER_COMPA] = { + .r_ocr = OCR3AL, + .r_ocrh = OCR3AH, // 16 bits timers have two bytes of it + .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3), + .com_pin = AVR_IO_REGBIT(PORTB, 6), + .interrupt = { + .enable = AVR_IO_REGBIT(TIMSK3, OCIE3A), + .raised = AVR_IO_REGBIT(TIFR3, OCF3A), + .vector = TIMER3_COMPA_vect, + } + }, + [AVR_TIMER_COMPB] = { + .r_ocr = OCR3BL, + .r_ocrh = OCR3BH, + .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3), + .com_pin = AVR_IO_REGBIT(PORTB, 7), + .interrupt = { + .enable = AVR_IO_REGBIT(TIMSK3, OCIE3B), + .raised = AVR_IO_REGBIT(TIFR3, OCF3B), + .vector = TIMER3_COMPB_vect, + } + } + } + }, +#endif .spi = { - .disabled = AVR_IO_REGBIT(PRR,PRSPI), + .disabled = AVR_IO_REGBIT(PRR0,PRSPI), .r_spdr = SPDR, .r_spcr = SPCR, @@ -399,7 +481,7 @@ const struct mcu_t SIM_CORENAME = { }, .twi = { - .disabled = AVR_IO_REGBIT(PRR,PRTWI), + .disabled = AVR_IO_REGBIT(PRR0,PRTWI), .r_twcr = TWCR, .r_twsr = TWSR, -- 2.39.5