From e175b0fd73521fd7acea6267bfe023a407f31da4 Mon Sep 17 00:00:00 2001
From: bsekisser <squirmyworms@embarqmail.com>
Date: Mon, 20 Oct 2014 14:06:49 -0400
Subject: [PATCH] cores: add spi declaration
convert spi structure definitions to AVR_SPI_DECLARE
modified: simavr/cores/sim_90usb162.c
modified: simavr/cores/sim_mega128.c
modified: simavr/cores/sim_mega1280.c
modified: simavr/cores/sim_mega1281.c
modified: simavr/cores/sim_mega128rfr2.c
modified: simavr/cores/sim_mega169.c
modified: simavr/cores/sim_mega2560.c
modified: simavr/cores/sim_megax.h
modified: simavr/cores/sim_megax4.h
modified: simavr/cores/sim_megax8.h
modified: simavr/cores/sim_megaxm1.h
modified: simavr/sim/avr_spi.h
---
simavr/cores/sim_90usb162.c | 17 +----------------
simavr/cores/sim_mega128.c | 18 +-----------------
simavr/cores/sim_mega1280.c | 19 +------------------
simavr/cores/sim_mega1281.c | 19 +------------------
simavr/cores/sim_mega128rfr2.c | 19 +------------------
simavr/cores/sim_mega169.c | 19 +------------------
simavr/cores/sim_mega2560.c | 19 +------------------
simavr/cores/sim_megax.h | 18 +-----------------
simavr/cores/sim_megax4.h | 19 +------------------
simavr/cores/sim_megax8.h | 19 +------------------
simavr/cores/sim_megaxm1.h | 19 +------------------
simavr/sim/avr_spi.h | 19 +++++++++++++++++++
12 files changed, 30 insertions(+), 194 deletions(-)
diff --git a/simavr/cores/sim_90usb162.c b/simavr/cores/sim_90usb162.c
index 3cdc647..577a45a 100644
--- a/simavr/cores/sim_90usb162.c
+++ b/simavr/cores/sim_90usb162.c
@@ -228,22 +228,7 @@ const struct mcu_t {
},
},
},
- .spi = {
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
+ AVR_SPI_DECLARE(0, 0),
.usb = {
.name='1',
.disabled=AVR_IO_REGBIT(PRR1, PRUSB),// bit in the PRR
diff --git a/simavr/cores/sim_mega128.c b/simavr/cores/sim_mega128.c
index 355b941..533dfcf 100644
--- a/simavr/cores/sim_mega128.c
+++ b/simavr/cores/sim_mega128.c
@@ -434,23 +434,7 @@ const struct mcu_t {
.vector = TIMER3_CAPT_vect,
},
},
- .spi = {
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(0, 0),
.twi = {
.r_twcr = TWCR,
diff --git a/simavr/cores/sim_mega1280.c b/simavr/cores/sim_mega1280.c
index 9ed040c..edbbf39 100644
--- a/simavr/cores/sim_mega1280.c
+++ b/simavr/cores/sim_mega1280.c
@@ -716,24 +716,7 @@ const struct mcu_t {
},
},
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(PRR0, PRSPI),
.twi = {
.r_twcr = TWCR,
diff --git a/simavr/cores/sim_mega1281.c b/simavr/cores/sim_mega1281.c
index a8a80bb..3378865 100644
--- a/simavr/cores/sim_mega1281.c
+++ b/simavr/cores/sim_mega1281.c
@@ -461,24 +461,7 @@ const struct mcu_t {
.vector = TIMER3_CAPT_vect,
},
},
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(PRR0, PRSPI),
.twi = {
.r_twcr = TWCR,
diff --git a/simavr/cores/sim_mega128rfr2.c b/simavr/cores/sim_mega128rfr2.c
index 2b0aab2..ffd9ad3 100644
--- a/simavr/cores/sim_mega128rfr2.c
+++ b/simavr/cores/sim_mega128rfr2.c
@@ -494,24 +494,7 @@ const struct mcu_t {
.vector = TIMER3_CAPT_vect,
},
},
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(PRR0, PRSPI),
.twi = {
.r_twcr = TWCR,
diff --git a/simavr/cores/sim_mega169.c b/simavr/cores/sim_mega169.c
index 93cb72b..41ee2aa 100644
--- a/simavr/cores/sim_mega169.c
+++ b/simavr/cores/sim_mega169.c
@@ -319,24 +319,7 @@ const struct mcu_t {
},
},
},
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(PRR, PRSPI),
};
static avr_t * make()
diff --git a/simavr/cores/sim_mega2560.c b/simavr/cores/sim_mega2560.c
index 4455bfe..12d0645 100644
--- a/simavr/cores/sim_mega2560.c
+++ b/simavr/cores/sim_mega2560.c
@@ -718,24 +718,7 @@ const struct mcu_t {
},
},
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(PRR0, PRSPI),
.twi = {
.r_twcr = TWCR,
diff --git a/simavr/cores/sim_megax.h b/simavr/cores/sim_megax.h
index 7d4379d..e2b00bf 100644
--- a/simavr/cores/sim_megax.h
+++ b/simavr/cores/sim_megax.h
@@ -288,23 +288,7 @@ const struct mcu_t SIM_CORENAME = {
},
},
},
- .spi = {
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(0, 0),
.twi = {
.r_twcr = TWCR,
diff --git a/simavr/cores/sim_megax4.h b/simavr/cores/sim_megax4.h
index a82fd3a..e579024 100644
--- a/simavr/cores/sim_megax4.h
+++ b/simavr/cores/sim_megax4.h
@@ -462,24 +462,7 @@ const struct mcu_t SIM_CORENAME = {
}
},
#endif
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(PRR0, PRSPI),
.twi = {
.disabled = AVR_IO_REGBIT(PRR0,PRTWI),
diff --git a/simavr/cores/sim_megax8.h b/simavr/cores/sim_megax8.h
index a1b2562..28d4def 100644
--- a/simavr/cores/sim_megax8.h
+++ b/simavr/cores/sim_megax8.h
@@ -336,24 +336,7 @@ const struct mcu_t SIM_CORENAME = {
}
}
},
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(PRR, PRSPI),
.twi = {
.disabled = AVR_IO_REGBIT(PRR,PRTWI),
diff --git a/simavr/cores/sim_megaxm1.h b/simavr/cores/sim_megaxm1.h
index 46c72fb..fdb929d 100644
--- a/simavr/cores/sim_megaxm1.h
+++ b/simavr/cores/sim_megaxm1.h
@@ -294,24 +294,7 @@ const struct mcu_t SIM_CORENAME = {
},
},
},
- .spi = {
- .disabled = AVR_IO_REGBIT(PRR,PRSPI),
-
- .r_spdr = SPDR,
- .r_spcr = SPCR,
- .r_spsr = SPSR,
-
- .spe = AVR_IO_REGBIT(SPCR, SPE),
- .mstr = AVR_IO_REGBIT(SPCR, MSTR),
-
- .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
- .spi = {
- .enable = AVR_IO_REGBIT(SPCR, SPIE),
- .raised = AVR_IO_REGBIT(SPSR, SPIF),
- .vector = SPI_STC_vect,
- },
- },
-
+ AVR_SPI_DECLARE(PRR, PRSPI),
};
#endif /* SIM_CORENAME */
diff --git a/simavr/sim/avr_spi.h b/simavr/sim/avr_spi.h
index 0f10252..79a1340 100644
--- a/simavr/sim/avr_spi.h
+++ b/simavr/sim/avr_spi.h
@@ -57,6 +57,25 @@ typedef struct avr_spi_t {
void avr_spi_init(avr_t * avr, avr_spi_t * port);
+#define AVR_SPI_DECLARE(_prr, _prspi) \
+ .spi = { \
+ .disabled = AVR_IO_REGBIT(_prr, _prspi), \
+ \
+ .r_spdr = SPDR, \
+ .r_spcr = SPCR, \
+ .r_spsr = SPSR, \
+ \
+ .spe = AVR_IO_REGBIT(SPCR, SPE), \
+ .mstr = AVR_IO_REGBIT(SPCR, MSTR), \
+ \
+ .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) }, \
+ .spi = { \
+ .enable = AVR_IO_REGBIT(SPCR, SPIE), \
+ .raised = AVR_IO_REGBIT(SPSR, SPIF), \
+ .vector = SPI_STC_vect, \
+ }, \
+ }
+
#ifdef __cplusplus
};
#endif
--
2.39.5