From f3ea05cd7e5b5c3f48e2a27394d8fc2d5acadaf2 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Tanel=20K=C3=BClaots?= Date: Thu, 5 Sep 2013 21:54:44 +0300 Subject: [PATCH] cores: Added atmega32 --- simavr/cores/sim_mega32.c | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 simavr/cores/sim_mega32.c diff --git a/simavr/cores/sim_mega32.c b/simavr/cores/sim_mega32.c new file mode 100644 index 0000000..40b74b4 --- /dev/null +++ b/simavr/cores/sim_mega32.c @@ -0,0 +1,45 @@ +/* + sim_mega324.c + + Copyright 2008, 2009 Michel Pollet + + This file is part of simavr. + + simavr is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + simavr is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with simavr. If not, see . + */ + +// atmega32 has different name for Watchdog Turn-off Enable register +#define WDCE WDTOE +#include "sim_avr.h" + +#define SIM_VECTOR_SIZE 4 +#define SIM_MMCU "atmega32" +#define SIM_CORENAME mcu_mega32 + +#define _AVR_IO_H_ +#define __ASSEMBLER__ +#include "avr/iom32.h" +// instantiate the new core +#include "sim_megax.h" + +static avr_t * make() +{ + return avr_core_allocate(&SIM_CORENAME.core, sizeof(struct mcu_t)); +} + +avr_kind_t mega32 = { + .names = { "atmega32", }, + .make = make +}; + -- 2.39.5